_FEATURE(sb,mask) \ EXT2_SB(sb)->s_es->s_feature_compat &= ~cpu_to_le32(mask) #define EXT2_CLEAR_RO_COMPAT_FEATURE(sb,mask) \ EXT2_SB(sb)->s_es->s_feature_ro_compat &= ~cpu_to_le32(mask) #define EXT2_CLEAR_INCOMPAT_FEATURE(sb,mask) \ EXT2_SB(sb)->s_es->s_feature_incompat &= ~cpu_to_le32(mask) #define EXT2_FEATURE_COMPAT_DIR_PREALLOC 0x0001 #define EXT2_FEATURE_COMPAT_IMAGIC_INODES 0x0002 #define EXT3_FEATURE_COMPAT_HAS_JOURNAL 0x0004 #define EXT2_FEATURE_COMPAT_EXT_ATTR 0x0008 #define EXT2_FEATURE_COMPAT_RESIZE_INO 0x0010 #define EXT2_FEATURE_COMPAT_DIR_INDEX 0x0020 #define EXT2_FEATURE_COMPAT_ANY 0xffffffff #define EXT2_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001 #define EXT2_FEATURE_RO_COMPAT_LARGE_FILE 0x0002 #define EXT2_FEATURE_RO_COMPAT_BTREE_DIR 0x0004 #define EXT2_FEATURE_RO_COMPAT_ANY 0xffffffff #define EXT2_FEATURE_INCOMPAT_COMPRESSION 0x0001 #define EXT2_FEATURE_INCOMPAT_FILETYPE 0x0002 #define EXT3_FEATURE_INCOMPAT_RECOVER 0x0004 #define EXT3_FEATURE_INCOMPAT_JOURNAL_DEV 0x0008 #define EXT2_FEATURE_INCOMPAT_META_BG 0x0010 #define EXT2_FEATURE_INCOMPAT_ANY 0xffffffff #define EXT2_FEATURE_COMPAT_SUPP EXT2_FEATURE_COMPAT_EXT_ATTR #define EXT2_FEATURE_INCOMPAT_SUPP (EXT2_FEATURE_INCOMPAT_FILETYPE| \ EXT2_FEATURE_INCOMPAT_META_BG) #define EXT2_FEATURE_RO_COMPAT_SUPP (EXT2_FEATURE_RO_COMPAT_SPARSE_SUPER| \ EXT2_FEATURE_RO_COMPAT_LARGE_FILE| \ EXT2_FEATURE_RO_COMPAT_BTREE_DIR) #define EXT2_FEATURE_RO_COMPAT_UNSUPPORTED ~EXT2_FEATURE_RO_COMPAT_SUPP #define EXT2_FEATURE_INCOMPAT_UNSUPPORTED ~EXT2_FEATURE_INCOMPAT_SUPP /* * Default values for user and/or group using reserved blocks */ #define EXT2_DEF_RESUID 0 #define EXT2_DEF_RESGID 0 /* * Default mount options */ #define EXT2_DEFM_DEBUG 0x0001 #define EXT2_DEFM_BSDGROUPS 0x0002 #define EXT2_DEFM_XATTR_USER 0x0004 #define EXT2_DEFM_ACL 0x0008 #define EXT2_DEFM_UID16 0x0010 /* Not used by ext2, but reserved for use by ext3 */ #define EXT3_DEFM_JMODE 0x0060 #define EXT3_DEFM_JMODE_DATA 0x0020 #define EXT3_DEFM_JMODE_ORDERED 0x0040 #define EXT3_DEFM_JMODE_WBACK 0x0060 /* * Structure of a directory entry */ #define EXT2_NAME_LEN 255 struct ext2_dir_entry { __le32 inode; /* Inode number */ __le16 rec_len; /* Directory entry length */ __le16 name_len; /* Name length */ char name[EXT2_NAME_LEN]; /* File name */ }; /* * The new version of the directory entry. Since EXT2 structures are * stored in intel byte order, and the name_len field could never be * bigger than 255 chars, it's safe to reclaim the extra byte for the * file_type field. */ struct ext2_dir_entry_2 { __le32 inode; /* Inode number */ __le16 rec_len; /* Directory entry length */ __u8 name_len; /* Name length */ __u8 file_type; char name[EXT2_NAME_LEN]; /* File name */ }; /* * Ext2 directory file types. Only the low 3 bits are used. The * other bits are reserved for now. */ enum { EXT2_FT_UNKNOWN = 0, EXT2_FT_REG_FILE = 1, EXT2_FT_DIR = 2, EXT2_FT_CHRDEV = 3, EXT2_FT_BLKDEV = 4, EXT2_FT_FIFO = 5, EXT2_FT_SOCK = 6, EXT2_FT_SYMLINK = 7, EXT2_FT_MAX }; /* * EXT2_DIR_PAD defines the directory entries boundaries * * NOTE: It must be a multiple of 4 */ #define EXT2_DIR_PAD 4 #define EXT2_DIR_ROUND (EXT2_DIR_PAD - 1) #define EXT2_DIR_REC_LEN(name_len) (((name_len) + 8 + EXT2_DIR_ROUND) & \ ~EXT2_DIR_ROUND) #define EXT2_MAX_REC_LEN ((1<<16)-1) #endif /* _LINUX_EXT2_FS_H */ /* * File: linux/nfsacl.h * * (C) 2003 Andreas Gruenbacher */ #ifndef __LINUX_NFSACL_H #define __LINUX_NFSACL_H #define NFS_ACL_PROGRAM 100227 #define ACLPROC2_GETACL 1 #define ACLPROC2_SETACL 2 #define ACLPROC2_GETATTR 3 #define ACLPROC2_ACCESS 4 #define ACLPROC3_GETACL 1 #define ACLPROC3_SETACL 2 /* Flags for the getacl/setacl mode */ #define NFS_ACL 0x0001 #define NFS_ACLCNT 0x0002 #define NFS_DFACL 0x0004 #define NFS_DFACLCNT 0x0008 /* Flag for Default ACL entries */ #define NFS_ACL_DEFAULT 0x1000 #endif /* __LINUX_NFSACL_H */ /* * include/linux/random.h * * Include file for the random number generator. */ #ifndef _LINUX_RANDOM_H #define _LINUX_RANDOM_H #include #include #include /* ioctl()'s for the random number generator */ /* Get the entropy count. */ #define RNDGETENTCNT _IOR( 'R', 0x00, int ) /* Add to (or subtract from) the entropy count. (Superuser only.) */ #define RNDADDTOENTCNT _IOW( 'R', 0x01, int ) /* Get the contents of the entropy pool. (Superuser only.) */ #define RNDGETPOOL _IOR( 'R', 0x02, int [2] ) /* * Write bytes into the entropy pool and add to the entropy count. * (Superuser only.) */ #define RNDADDENTROPY _IOW( 'R', 0x03, int [2] ) /* Clear entropy count to 0. (Superuser only.) */ #define RNDZAPENTCNT _IO( 'R', 0x04 ) /* Clear the entropy pool and associated counters. (Superuser only.) */ #define RNDCLEARPOOL _IO( 'R', 0x06 ) struct rand_pool_info { int entropy_count; int buf_size; __u32 buf[0]; }; struct rnd_state { __u32 s1, s2, s3; }; /* Exported functions */ #endif /* _LINUX_RANDOM_H */ /* * NFS protocol definitions * * This file contains constants for Version 2 of the protocol. */ #ifndef _LINUX_NFS2_H #define _LINUX_NFS2_H #define NFS2_PORT 2049 #define NFS2_MAXDATA 8192 #define NFS2_MAXPATHLEN 1024 #define NFS2_MAXNAMLEN 255 #define NFS2_MAXGROUPS 16 #define NFS2_FHSIZE 32 #define NFS2_COOKIESIZE 4 #define NFS2_FIFO_DEV (-1) #define NFS2MODE_FMT 0170000 #define NFS2MODE_DIR 0040000 #define NFS2MODE_CHR 0020000 #define NFS2MODE_BLK 0060000 #define NFS2MODE_REG 0100000 #define NFS2MODE_LNK 0120000 #define NFS2MODE_SOCK 0140000 #define NFS2MODE_FIFO 0010000 /* NFSv2 file types - beware, these are not the same in NFSv3 */ enum nfs2_ftype { NF2NON = 0, NF2REG = 1, NF2DIR = 2, NF2BLK = 3, NF2CHR = 4, NF2LNK = 5, NF2SOCK = 6, NF2BAD = 7, NF2FIFO = 8 }; struct nfs2_fh { char data[NFS2_FHSIZE]; }; /* * Procedure numbers for NFSv2 */ #define NFS2_VERSION 2 #define NFSPROC_NULL 0 #define NFSPROC_GETATTR 1 #define NFSPROC_SETATTR 2 #define NFSPROC_ROOT 3 #define NFSPROC_LOOKUP 4 #define NFSPROC_READLINK 5 #define NFSPROC_READ 6 #define NFSPROC_WRITECACHE 7 #define NFSPROC_WRITE 8 #define NFSPROC_CREATE 9 #define NFSPROC_REMOVE 10 #define NFSPROC_RENAME 11 #define NFSPROC_LINK 12 #define NFSPROC_SYMLINK 13 #define NFSPROC_MKDIR 14 #define NFSPROC_RMDIR 15 #define NFSPROC_READDIR 16 #define NFSPROC_STATFS 17 #endif /* _LINUX_NFS2_H */ /* atm.h - general ATM declarations */ /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ /* * WARNING: User-space programs should not #include directly. * Instead, #include */ #ifndef _LINUX_ATM_H #define _LINUX_ATM_H /* * BEGIN_xx and END_xx markers are used for automatic generation of * documentation. Do not change them. */ #include #include #include #include /* general ATM constants */ #define ATM_CELL_SIZE 53 /* ATM cell size incl. header */ #define ATM_CELL_PAYLOAD 48 /* ATM payload size */ #define ATM_AAL0_SDU 52 /* AAL0 SDU size */ #define ATM_MAX_AAL34_PDU 65535 /* maximum AAL3/4 PDU payload */ #define ATM_AAL5_TRAILER 8 /* AAL5 trailer size */ #define ATM_MAX_AAL5_PDU 65535 /* maximum AAL5 PDU payload */ #define ATM_MAX_CDV 9999 /* maximum (default) CDV */ #define ATM_NOT_RSV_VCI 32 /* first non-reserved VCI value */ #define ATM_MAX_VPI 255 /* maximum VPI at the UNI */ #define ATM_MAX_VPI_NNI 4096 /* maximum VPI at the NNI */ #define ATM_MAX_VCI 65535 /* maximum VCI */ /* "protcol" values for the socket system call */ #define ATM_NO_AAL 0 /* AAL not specified */ #define ATM_AAL0 13 /* "raw" ATM cells */ #define ATM_AAL1 1 /* AAL1 (CBR) */ #define ATM_AAL2 2 /* AAL2 (VBR) */ #define ATM_AAL34 3 /* AAL3/4 (data) */ #define ATM_AAL5 5 /* AAL5 (data) */ /* * socket option name coding functions * * Note that __SO_ENCODE and __SO_LEVEL are somewhat a hack since the * << 22 only reserves 9 bits for the level. On some architectures * SOL_SOCKET is 0xFFFF, so that's a bit of a problem */ #define __SO_ENCODE(l,n,t) ((((l) & 0x1FF) << 22) | ((n) << 16) | \ sizeof(t)) #define __SO_LEVEL_MATCH(c,m) (((c) >> 22) == ((m) & 0x1FF)) #define __SO_NUMBER(c) (((c) >> 16) & 0x3f) #define __SO_SIZE(c) ((c) & 0x3fff) /* * ATM layer */ #define SO_SETCLP __SO_ENCODE(SOL_ATM,0,int) /* set CLP bit value - TODO */ #define SO_CIRANGE __SO_ENCODE(SOL_ATM,1,struct atm_cirange) /* connection identifier range; socket must be bound or connected */ #define SO_ATMQOS __SO_ENCODE(SOL_ATM,2,struct atm_qos) /* Quality of Service setting */ #define SO_ATMSAP __SO_ENCODE(SOL_ATM,3,struct atm_sap) /* Service Access Point */ #define SO_ATMPVC __SO_ENCODE(SOL_ATM,4,struct sockaddr_atmpvc) /* "PVC" address (also for SVCs); get only */ #define SO_MULTIPOINT __SO_ENCODE(SOL_ATM, 5, int) /* make this vc a p2mp */ /* * Note @@@: since the socket layers don't really distinguish the control and * the data plane but generally seems to be data plane-centric, any layer is * about equally wrong for the SAP. If you have a better idea about this, * please speak up ... */ /* ATM cell header (for AAL0) */ /* BEGIN_CH */ #define ATM_HDR_GFC_MASK 0xf0000000 #define ATM_HDR_GFC_SHIFT 28 #define ATM_HDR_VPI_MASK 0x0ff00000 #define ATM_HDR_VPI_SHIFT 20 #define ATM_HDR_VCI_MASK 0x000ffff0 #define ATM_HDR_VCI_SHIFT 4 #define ATM_HDR_PTI_MASK 0x0000000e #define ATM_HDR_PTI_SHIFT 1 #define ATM_HDR_CLP 0x00000001 /* END_CH */ /* PTI codings */ /* BEGIN_PTI */ #define ATM_PTI_US0 0 /* user data cell, congestion not exp, SDU-type 0 */ #define ATM_PTI_US1 1 /* user data cell, congestion not exp, SDU-type 1 */ #define ATM_PTI_UCES0 2 /* user data cell, cong. experienced, SDU-type 0 */ #define ATM_PTI_UCES1 3 /* user data cell, cong. experienced, SDU-type 1 */ #define ATM_PTI_SEGF5 4 /* segment OAM F5 flow related cell */ #define ATM_PTI_E2EF5 5 /* end-to-end OAM F5 flow related cell */ #define ATM_PTI_RSV_RM 6 /* reserved for traffic control/resource mgmt */ #define ATM_PTI_RSV 7 /* reserved */ /* END_PTI */ /* * The following items should stay in linux/atm.h, which should be linked to * netatm/atm.h */ /* Traffic description */ #define ATM_NONE 0 /* no traffic */ #define ATM_UBR 1 #define ATM_CBR 2 #define ATM_VBR 3 #define ATM_ABR 4 #define ATM_ANYCLASS 5 /* compatible with everything */ #define ATM_MAX_PCR -1 /* maximum available PCR */ struct atm_trafprm { unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */ int max_pcr; /* maximum PCR in cells per second */ int pcr; /* desired PCR in cells per second */ int min_pcr; /* minimum PCR in cells per second */ int max_cdv; /* maximum CDV in microseconds */ int max_sdu; /* maximum SDU in bytes */ /* extra params for ABR */ unsigned int icr; /* Initial Cell Rate (24-bit) */ unsigned int tbe; /* Transient Buffer Exposure (24-bit) */ unsigned int frtt : 24; /* Fixed Round Trip Time (24-bit) */ unsigned int rif : 4; /* Rate Increment Factor (4-bit) */ unsigned int rdf : 4; /* Rate Decrease Factor (4-bit) */ unsigned int nrm_pres :1; /* nrm present bit */ unsigned int trm_pres :1; /* rm present bit */ unsigned int adtf_pres :1; /* adtf present bit */ unsigned int cdf_pres :1; /* cdf present bit*/ unsigned int nrm :3; /* Max # of Cells for each forward RM cell (3-bit) */ unsigned int trm :3; /* Time between forward RM cells (3-bit) */ unsigned int adtf :10; /* ACR Decrease Time Factor (10-bit) */ unsigned int cdf :3; /* Cutoff Decrease Factor (3-bit) */ unsigned int spare :9; /* spare bits */ }; struct atm_qos { struct atm_trafprm txtp; /* parameters in TX direction */ struct atm_trafprm rxtp __ATM_API_ALIGN; /* parameters in RX direction */ unsigned char aal __ATM_API_ALIGN; }; /* PVC addressing */ #define ATM_ITF_ANY -1 /* "magic" PVC address values */ #define ATM_VPI_ANY -1 #define ATM_VCI_ANY -1 #define ATM_VPI_UNSPEC -2 #define ATM_VCI_UNSPEC -2 struct sockaddr_atmpvc { unsigned short sap_family; /* address family, AF_ATMPVC */ struct { /* PVC address */ short itf; /* ATM interface */ short vpi; /* VPI (only 8 bits at UNI) */ int vci; /* VCI (only 16 bits at UNI) */ } sap_addr __ATM_API_ALIGN; /* PVC address */ }; /* SVC addressing */ #define ATM_ESA_LEN 20 /* ATM End System Address length */ #define ATM_E164_LEN 12 /* maximum E.164 number length */ #define ATM_AFI_DCC 0x39 /* DCC ATM Format */ #define ATM_AFI_ICD 0x47 /* ICD ATM Format */ #define ATM_AFI_E164 0x45 /* E.164 ATM Format */ #define ATM_AFI_LOCAL 0x49 /* Local ATM Format */ #define ATM_AFI_DCC_GROUP 0xBD /* DCC ATM Group Format */ #define ATM_AFI_ICD_GROUP 0xC5 /* ICD ATM Group Format */ #define ATM_AFI_E164_GROUP 0xC3 /* E.164 ATM Group Format */ #define ATM_AFI_LOCAL_GROUP 0xC7 /* Local ATM Group Format */ #define ATM_LIJ_NONE 0 /* no leaf-initiated join */ #define ATM_LIJ 1 /* request joining */ #define ATM_LIJ_RPJ 2 /* set to root-prompted join */ #define ATM_LIJ_NJ 3 /* set to network join */ struct sockaddr_atmsvc { unsigned short sas_family; /* address family, AF_ATMSVC */ struct { /* SVC address */ unsigned char prv[ATM_ESA_LEN];/* private ATM address */ char pub[ATM_E164_LEN+1]; /* public address (E.164) */ /* unused addresses must be bzero'ed */ char lij_type; /* role in LIJ call; one of ATM_LIJ* */ __u32 lij_id; /* LIJ call identifier */ } sas_addr __ATM_API_ALIGN; /* SVC address */ }; static __inline__ int atmsvc_addr_in_use(struct sockaddr_atmsvc addr) { return *addr.sas_addr.prv || *addr.sas_addr.pub; } static __inline__ int atmpvc_addr_in_use(struct sockaddr_atmpvc addr) { return addr.sap_addr.itf || addr.sap_addr.vpi || addr.sap_addr.vci; } /* * Some stuff for linux/sockios.h */ struct atmif_sioc { int number; int length; void *arg; }; typedef unsigned short atm_backend_t; #endif /* * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. * * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */ #ifndef _LINUX_SERIAL_REG_H #define _LINUX_SERIAL_REG_H /* * DLAB=0 */ #define UART_RX 0 /* In: Receive buffer */ #define UART_TX 0 /* Out: Transmit buffer */ #define UART_IER 1 /* Out: Interrupt Enable Register */ #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ /* * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 */ #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ #define UART_IIR 2 /* In: Interrupt ID Register */ #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ #define UART_IIR_MSI 0x00 /* Modem status interrupt */ #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ #define UART_FCR 2 /* Out: FIFO Control Register */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ /* * Note: The FIFO trigger levels are chip specific: * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 * PC16550D: 1 4 8 14 xx xx xx xx * TI16C550A: 1 4 8 14 xx xx xx xx * TI16C550C: 1 4 8 14 xx xx xx xx * ST16C550: 1 4 8 14 xx xx xx xx * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 * NS16C552: 1 4 8 14 xx xx xx xx * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 * TI16C752: 8 16 56 60 8 16 32 56 */ #define UART_FCR_R_TRIG_00 0x00 #define UART_FCR_R_TRIG_01 0x40 #define UART_FCR_R_TRIG_10 0x80 #define UART_FCR_R_TRIG_11 0xc0 #define UART_FCR_T_TRIG_00 0x00 #define UART_FCR_T_TRIG_01 0x10 #define UART_FCR_T_TRIG_10 0x20 #define UART_FCR_T_TRIG_11 0x30 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ /* 16650 definitions */ #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ #define UART_LCR 3 /* Out: Line Control Register */ /* * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ #define UART_LCR_SBC 0x40 /* Set break control */ #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ #define UART_LCR_EPAR 0x10 /* Even parity select */ #define UART_LCR_PARITY 0x08 /* Parity Enable */ #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ #define UART_MCR_RTS 0x02 /* RTS complement */ #define UART_MCR_DTR 0x01 /* DTR complement */ #define UART_LSR 5 /* In: Line Status Register */ #define UART_LSR_TEMT 0x40 /* Transmitter empty */ #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define UART_LSR_BI 0x10 /* Break interrupt indicator */ #define UART_LSR_FE 0x08 /* Frame error indicator */ #define UART_LSR_PE 0x04 /* Parity error indicator */ #define UART_LSR_OE 0x02 /* Overrun error indicator */ #define UART_LSR_DR 0x01 /* Receiver data ready */ #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ #define UART_MSR 6 /* In: Modem Status Register */ #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ #define UART_MSR_RI 0x40 /* Ring Indicator */ #define UART_MSR_DSR 0x20 /* Data Set Ready */ #define UART_MSR_CTS 0x10 /* Clear to Send */ #define UART_MSR_DDCD 0x08 /* Delta DCD */ #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ #define UART_MSR_DDSR 0x02 /* Delta DSR */ #define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ #define UART_SCR 7 /* I/O: Scratch Register */ /* * DLAB=1 */ #define UART_DLL 0 /* Out: Divisor Latch Low */ #define UART_DLM 1 /* Out: Divisor Latch High */ /* * LCR=0xBF (or DLAB=1 for 16C660) */ #define UART_EFR 2 /* I/O: Extended Features Register */ #define UART_EFR_CTS 0x80 /* CTS flow control */ #define UART_EFR_RTS 0x40 /* RTS flow control */ #define UART_EFR_SCD 0x20 /* Special character detect */ #define UART_EFR_ECB 0x10 /* Enhanced control bit */ /* * the low four bits control software flow control */ /* * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 */ #define UART_XON1 4 /* I/O: Xon character 1 */ #define UART_XON2 5 /* I/O: Xon character 2 */ #define UART_XOFF1 6 /* I/O: Xoff character 1 */ #define UART_XOFF2 7 /* I/O: Xoff character 2 */ /* * EFR[4]=1 MCR[6]=1, TI16C752 */ #define UART_TI752_TCR 6 /* I/O: transmission control register */ #define UART_TI752_TLR 7 /* I/O: trigger level register */ /* * LCR=0xBF, XR16C85x */ #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx * In: Fifo count * Out: Fifo custom trigger levels */ /* * These are the definitions for the Programmable Trigger Register */ #define UART_TRG_1 0x01 #define UART_TRG_4 0x04 #define UART_TRG_8 0x08 #define UART_TRG_16 0x10 #define UART_TRG_32 0x20 #define UART_TRG_64 0x40 #define UART_TRG_96 0x60 #define UART_TRG_120 0x78 #define UART_TRG_128 0x80 #define UART_FCTR 1 /* Feature Control Register */ #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ #define UART_FCTR_RTS_4DELAY 0x01 #define UART_FCTR_RTS_6DELAY 0x02 #define UART_FCTR_RTS_8DELAY 0x03 #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ /* * LCR=0xBF, FCTR[6]=1 */ #define UART_EMSR 7 /* Extended Mode Select Register */ #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ /* * The Intel XScale on-chip UARTs define these bits */ #define UART_IER_DMAE 0x80 /* DMA Requests Enable */ #define UART_IER_UUE 0x40 /* UART Unit Enable */ #define UART_IER_NRZE 0x20 /* NRZ coding Enable */ #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ /* * Intel MID on-chip HSU (High Speed UART) defined bits */ #define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ #define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ #define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ #define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ #define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ #define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ #define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ #define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ #define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ #define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ #define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ /* * These register definitions are for the 16C950 */ #define UART_ASR 0x01 /* Additional Status Register */ #define UART_RFL 0x03 /* Receiver FIFO level */ #define UART_TFL 0x04 /* Transmitter FIFO level */ #define UART_ICR 0x05 /* Index Control Register */ /* The 16950 ICR registers */ #define UART_ACR 0x00 /* Additional Control Register */ #define UART_CPR 0x01 /* Clock Prescalar Register */ #define UART_TCR 0x02 /* Times Clock Register */ #define UART_CKS 0x03 /* Clock Select Register */ #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ #define UART_FCL 0x06 /* Flow Control Level Lower */ #define UART_FCH 0x07 /* Flow Control Level Higher */ #define UART_ID1 0x08 /* ID #1 */ #define UART_ID2 0x09 /* ID #2 */ #define UART_ID3 0x0A /* ID #3 */ #define UART_REV 0x0B /* Revision */ #define UART_CSR 0x0C /* Channel Software Reset */ #define UART_NMR 0x0D /* Nine-bit Mode Register */ #define UART_CTR 0xFF /* * The 16C950 Additional Control Register */ #define UART_ACR_RXDIS 0x01 /* Receiver disable */ #define UART_ACR_TXDIS 0x02 /* Transmitter disable */ #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ #define UART_ACR_ASREN 0x80 /* Additional status enable */ /* * These definitions are for the RSA-DV II/S card, from * * Kiyokazu SUTO */ #define UART_RSA_BASE (-8) #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /*ßß Tx FIFO is not empty (1) */ #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ /* * The RSA DSV/II board has two fixed clock frequencies. One is the * standard rate, and the other is 8 times faster. */ #define SERIAL_RSA_BAUD_BASE (921600) #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) /* * Extra serial register definitions for the internal UARTs * in TI OMAP processors. */ #define UART_OMAP_MDR1 0x08 /* Mode definition register */ #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ #define UART_OMAP_SCR 0x10 /* Supplementary control register */ #define UART_OMAP_SSR 0x11 /* Supplementary status register */ #define UART_OMAP_EBLR 0x12 /* BOF length register */ #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ #define UART_OMAP_MVER 0x14 /* Module version register */ #define UART_OMAP_SYSC 0x15 /* System configuration register */ #define UART_OMAP_SYSS 0x16 /* System status register */ #define UART_OMAP_WER 0x17 /* Wake-up enable register */ #endif /* _LINUX_SERIAL_REG_H */ #ifndef _LINUX_MSG_H #define _LINUX_MSG_H #include /* ipcs ctl commands */ #define MSG_STAT 11 #define MSG_INFO 12 /* msgrcv options */ #define MSG_NOERROR 010000 /* no error if message is too big */ #define MSG_EXCEPT 020000 /* recv any msg except of specified type.*/ /* Obsolete, used only for backwards compatibility and libc5 compiles */ struct msqid_ds { struct ipc_perm msg_perm; struct msg *msg_first; /* first message on queue,unused */ struct msg *msg_last; /* last message in queue,unused */ __kernel_time_t msg_stime; /* last msgsnd time */ __kernel_time_t msg_rtime; /* last msgrcv time */ __kernel_time_t msg_ctime; /* last change time */ unsigned long msg_lcbytes; /* Reuse junk fields for 32 bit */ unsigned long msg_lqbytes; /* ditto */ unsigned short msg_cbytes; /* current number of bytes on queue */ unsigned short msg_qnum; /* number of messages in queue */ unsigned short msg_qbytes; /* max number of bytes on queue */ __kernel_ipc_pid_t msg_lspid; /* pid of last msgsnd */ __kernel_ipc_pid_t msg_lrpid; /* last receive pid */ }; /* Include the definition of msqid64_ds */ #include /* message buffer for msgsnd and msgrcv calls */ struct msgbuf { long mtype; /* type of message */ char mtext[1]; /* message text */ }; /* buffer for msgctl calls IPC_INFO, MSG_INFO */ struct msginfo { int msgpool; int msgmap; int msgmax; int msgmnb; int msgmni; int msgssz; int msgtql; unsigned short msgseg; }; /* * Scaling factor to compute msgmni: * the memory dedicated to msg queues (msgmni * msgmnb) should occupy * at most 1/MSG_MEM_SCALE of the lowmem (see the formula in ipc/msg.c): * up to 8MB : msgmni = 16 (MSGMNI) * 4 GB : msgmni = 8K * more than 16 GB : msgmni = 32K (IPCMNI) */ #define MSG_MEM_SCALE 32 #define MSGMNI 16 /* <= IPCMNI */ /* max # of msg queue identifiers */ #define MSGMAX 8192 /* <= INT_MAX */ /* max size of message (bytes) */ #define MSGMNB 16384 /* <= INT_MAX */ /* default max size of a message queue */ /* unused */ #define MSGPOOL (MSGMNI * MSGMNB / 1024) /* size in kbytes of message pool */ #define MSGTQL MSGMNB /* number of system message headers */ #define MSGMAP MSGMNB /* number of entries in message map */ #define MSGSSZ 16 /* message segment size */ #define __MSGSEG ((MSGPOOL * 1024) / MSGSSZ) /* max no. of segments */ #define MSGSEG (__MSGSEG <= 0xffff ? __MSGSEG : 0xffff) #endif /* _LINUX_MSG_H */ /* * Video for Linux version 1 - OBSOLETE * * Header file for v4l1 drivers and applications, for * Linux kernels 2.2.x or 2.4.x. * * Provides header for legacy drivers and applications * * See http://linuxtv.org for more info * */ #ifndef __LINUX_VIDEODEV_H #define __LINUX_VIDEODEV_H #include #include #include #define VID_TYPE_CAPTURE 1 /* Can capture */ #define VID_TYPE_TUNER 2 /* Can tune */ #define VID_TYPE_TELETEXT 4 /* Does teletext */ #define VID_TYPE_OVERLAY 8 /* Overlay onto frame buffer */ #define VID_TYPE_CHROMAKEY 16 /* Overlay by chromakey */ #define VID_TYPE_CLIPPING 32 /* Can clip */ #define VID_TYPE_FRAMERAM 64 /* Uses the frame buffer memory */ #define VID_TYPE_SCALES 128 /* Scalable */ #define VID_TYPE_MONOCHROME 256 /* Monochrome only */ #define VID_TYPE_SUBCAPTURE 512 /* Can capture subareas of the image */ #define VID_TYPE_MPEG_DECODER 1024 /* Can decode MPEG streams */ #define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */ #define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */ #define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */ struct video_capability { char name[32]; int type; int channels; /* Num channels */ int audios; /* Num audio devices */ int maxwidth; /* Supported width */ int maxheight; /* And height */ int minwidth; /* Supported width */ int minheight; /* And height */ }; struct video_channel { int channel; char name[32]; int tuners; __u32 flags; #define VIDEO_VC_TUNER 1 /* Channel has a tuner */ #define VIDEO_VC_AUDIO 2 /* Channel has audio */ __u16 type; #define VIDEO_TYPE_TV 1 #define VIDEO_TYPE_CAMERA 2 __u16 norm; /* Norm set by channel */ }; struct video_tuner { int tuner; char name[32]; unsigned long rangelow, rangehigh; /* Tuner range */ __u32 flags; #define VIDEO_TUNER_PAL 1 #define VIDEO_TUNER_NTSC 2 #define VIDEO_TUNER_SECAM 4 #define VIDEO_TUNER_LOW 8 /* Uses KHz not MHz */ #define VIDEO_TUNER_NORM 16 /* Tuner can set norm */ #define VIDEO_TUNER_STEREO_ON 128 /* Tuner is seeing stereo */ #define VIDEO_TUNER_RDS_ON 256 /* Tuner is seeing an RDS datastream */ #define VIDEO_TUNER_MBS_ON 512 /* Tuner is seeing an MBS datastream */ __u16 mode; /* PAL/NTSC/SECAM/OTHER */ #define VIDEO_MODE_PAL 0 #define VIDEO_MODE_NTSC 1 #define VIDEO_MODE_SECAM 2 #define VIDEO_MODE_AUTO 3 __u16 signal; /* Signal strength 16bit scale */ }; struct video_picture { __u16 brightness; __u16 hue; __u16 colour; __u16 contrast; __u16 whiteness; /* Black and white only */ __u16 depth; /* Capture depth */ __u16 palette; /* Palette in use */ #define VIDEO_PALETTE_GREY 1 /* Linear greyscale */ #define VIDEO_PALETTE_HI240 2 /* High 240 cube (BT848) */ #define VIDEO_PALETTE_RGB565 3 /* 565 16 bit RGB */ #define VIDEO_PALETTE_RGB24 4 /* 24bit RGB */ #define VIDEO_PALETTE_RGB32 5 /* 32bit RGB */ #define VIDEO_PALETTE_RGB555 6 /* 555 15bit RGB */ #define VIDEO_PALETTE_YUV422 7 /* YUV422 capture */ #define VIDEO_PALETTE_YUYV 8 #define VIDEO_PALETTE_UYVY 9 /* The great thing about standards is ... */ #define VIDEO_PALETTE_YUV420 10 #define VIDEO_PALETTE_YUV411 11 /* YUV411 capture */ #define VIDEO_PALETTE_RAW 12 /* RAW capture (BT848) */ #define VIDEO_PALETTE_YUV422P 13 /* YUV 4:2:2 Planar */ #define VIDEO_PALETTE_YUV411P 14 /* YUV 4:1:1 Planar */ #define VIDEO_PALETTE_YUV420P 15 /* YUV 4:2:0 Planar */ #define VIDEO_PALETTE_YUV410P 16 /* YUV 4:1:0 Planar */ #define VIDEO_PALETTE_PLANAR 13 /* start of planar entries */ #define VIDEO_PALETTE_COMPONENT 7 /* start of component entries */ }; struct video_audio { int audio; /* Audio channel */ __u16 volume; /* If settable */ __u16 bass, treble; __u32 flags; #define VIDEO_AUDIO_MUTE 1 #define VIDEO_AUDIO_MUTABLE 2 #define VIDEO_AUDIO_VOLUME 4 #define VIDEO_AUDIO_BASS 8 #define VIDEO_AUDIO_TREBLE 16 #define VIDEO_AUDIO_BALANCE 32 char name[16]; #define VIDEO_SOUND_MONO 1 #define VIDEO_SOUND_STEREO 2 #define VIDEO_SOUND_LANG1 4 #define VIDEO_SOUND_LANG2 8 __u16 mode; __u16 balance; /* Stereo balance */ __u16 step; /* Step actual volume uses */ }; struct video_clip { __s32 x,y; __s32 width, height; struct video_clip *next; /* For user use/driver use only */ }; struct video_window { __u32 x,y; /* Position of window */ __u32 width,height; /* Its size */ __u32 chromakey; __u32 flags; struct video_clip *clips; /* Set only */ int clipcount; #define VIDEO_WINDOW_INTERLACE 1 #define VIDEO_WINDOW_CHROMAKEY 16 /* Overlay by chromakey */ #define VIDEO_CLIP_BITMAP -1 /* bitmap is 1024x625, a '1' bit represents a clipped pixel */ #define VIDEO_CLIPMAP_SIZE (128 * 625) }; struct video_capture { __u32 x,y; /* Offsets into image */ __u32 width, height; /* Area to capture */ __u16 decimation; /* Decimation divider */ __u16 flags; /* Flags for capture */ #define VIDEO_CAPTURE_ODD 0 /* Temporal */ #define VIDEO_CAPTURE_EVEN 1 }; struct video_buffer { void *base; int height,width; int depth; int bytesperline; }; struct video_mmap { unsigned int frame; /* Frame (0 - n) for double buffer */ int height,width; unsigned int format; /* should be VIDEO_PALETTE_* */ }; struct video_key { __u8 key[8]; __u32 flags; }; struct video_mbuf { int size; /* Total memory to map */ int frames; /* Frames */ int offsets[VIDEO_MAX_FRAME]; }; #define VIDEO_NO_UNIT (-1) struct video_unit { int video; /* Video minor */ int vbi; /* VBI minor */ int radio; /* Radio minor */ int audio; /* Audio minor */ int teletext; /* Teletext minor */ }; struct vbi_format { __u32 sampling_rate; /* in Hz */ __u32 samples_per_line; __u32 sample_format; /* VIDEO_PALETTE_RAW only (1 byte) */ __s32 start[2]; /* starting line for each frame */ __u32 count[2]; /* count of lines for each frame */ __u32 flags; #define VBI_UNSYNC 1 /* can distingues between top/bottom field */ #define VBI_INTERLACED 2 /* lines are interlaced */ }; /* video_info is biased towards hardware mpeg encode/decode */ /* but it could apply generically to any hardware compressor/decompressor */ struct video_info { __u32 frame_count; /* frames output since decode/encode began */ __u32 h_size; /* current unscaled horizontal size */ __u32 v_size; /* current unscaled veritcal size */ __u32 smpte_timecode; /* current SMPTE timecode (for current GOP) */ __u32 picture_type; /* current picture type */ __u32 temporal_reference; /* current temporal reference */ __u8 user_data[256]; /* user data last found in compressed stream */ /* user_data[0] contains user data flags, user_data[1] has count */ }; /* generic structure for setting playback modes */ struct video_play_mode { int mode; int p1; int p2; }; /* for loading microcode / fpga programming */ struct video_code { char loadwhat[16]; /* name or tag of file being passed */ int datasize; __u8 *data; }; #define VIDIOCGCAP _IOR('v',1,struct video_capability) /* Get capabilities */ #define VIDIOCGCHAN _IOWR('v',2,struct video_channel) /* Get channel info (sources) */ #define VIDIOCSCHAN _IOW('v',3,struct video_channel) /* Set channel */ #define VIDIOCGTUNER _IOWR('v',4,struct video_tuner) /* Get tuner abilities */ #define VIDIOCSTUNER _IOW('v',5,struct video_tuner) /* Tune the tuner for the current channel */ #define VIDIOCGPICT _IOR('v',6,struct video_picture) /* Get picture properties */ #define VIDIOCSPICT _IOW('v',7,struct video_picture) /* Set picture properties */ #define VIDIOCCAPTURE _IOW('v',8,int) /* Start, end capture */ #define VIDIOCGWIN _IOR('v',9, struct video_window) /* Get the video overlay window */ #define VIDIOCSWIN _IOW('v',10, struct video_window) /* Set the video overlay window - passes clip list for hardware smarts , chromakey etc */ #define VIDIOCGFBUF _IOR('v',11, struct video_buffer) /* Get frame buffer */ #define VIDIOCSFBUF _IOW('v',12, struct video_buffer) /* Set frame buffer - root only */ #define VIDIOCKEY _IOR('v',13, struct video_key) /* Video key event - to dev 255 is to all - cuts capture on all DMA windows with this key (0xFFFFFFFF == all) */ #define VIDIOCGFREQ _IOR('v',14, unsigned long) /* Set tuner */ #define VIDIOCSFREQ _IOW('v',15, unsigned long) /* Set tuner */ #define VIDIOCGAUDIO _IOR('v',16, struct video_audio) /* Get audio info */ #define VIDIOCSAUDIO _IOW('v',17, struct video_audio) /* Audio source, mute etc */ #define VIDIOCSYNC _IOW('v',18, int) /* Sync with mmap grabbing */ #define VIDIOCMCAPTURE _IOW('v',19, struct video_mmap) /* Grab frames */ #define VIDIOCGMBUF _IOR('v',20, struct video_mbuf) /* Memory map buffer info */ #define VIDIOCGUNIT _IOR('v',21, struct video_unit) /* Get attached units */ #define VIDIOCGCAPTURE _IOR('v',22, struct video_capture) /* Get subcapture */ #define VIDIOCSCAPTURE _IOW('v',23, struct video_capture) /* Set subcapture */ #define VIDIOCSPLAYMODE _IOW('v',24, struct video_play_mode) /* Set output video mode/feature */ #define VIDIOCSWRITEMODE _IOW('v',25, int) /* Set write mode */ #define VIDIOCGPLAYINFO _IOR('v',26, struct video_info) /* Get current playback info from hardware */ #define VIDIOCSMICROCODE _IOW('v',27, struct video_code) /* Load microcode into hardware */ #define VIDIOCGVBIFMT _IOR('v',28, struct vbi_format) /* Get VBI information */ #define VIDIOCSVBIFMT _IOW('v',29, struct vbi_format) /* Set VBI information */ #define BASE_VIDIOCPRIVATE 192 /* 192-255 are private */ /* VIDIOCSWRITEMODE */ #define VID_WRITE_MPEG_AUD 0 #define VID_WRITE_MPEG_VID 1 #define VID_WRITE_OSD 2 #define VID_WRITE_TTX 3 #define VID_WRITE_CC 4 #define VID_WRITE_MJPEG 5 /* VIDIOCSPLAYMODE */ #define VID_PLAY_VID_OUT_MODE 0 /* p1: = VIDEO_MODE_PAL, VIDEO_MODE_NTSC, etc ... */ #define VID_PLAY_GENLOCK 1 /* p1: 0 = OFF, 1 = ON */ /* p2: GENLOCK FINE DELAY value */ #define VID_PLAY_NORMAL 2 #define VID_PLAY_PAUSE 3 #define VID_PLAY_SINGLE_FRAME 4 #define VID_PLAY_FAST_FORWARD 5 #define VID_PLAY_SLOW_MOTION 6 #define VID_PLAY_IMMEDIATE_NORMAL 7 #define VID_PLAY_SWITCH_CHANNELS 8 #define VID_PLAY_FREEZE_FRAME 9 #define VID_PLAY_STILL_MODE 10 #define VID_PLAY_MASTER_MODE 11 /* p1: see below */ #define VID_PLAY_MASTER_NONE 1 #define VID_PLAY_MASTER_VIDEO 2 #define VID_PLAY_MASTER_AUDIO 3 #define VID_PLAY_ACTIVE_SCANLINES 12 /* p1 = first active; p2 = last active */ #define VID_PLAY_RESET 13 #define VID_PLAY_END_MARK 14 #endif /* __LINUX_VIDEODEV_H */ /* * Local variables: * c-basic-offset: 8 * End: */ #ifndef _LINUX_APM_H #define _LINUX_APM_H /* * Include file for the interface to an APM BIOS * Copyright 1994-2001 Stephen Rothwell (sfr@canb.auug.org.au) * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2, or (at your option) any * later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. */ #include typedef unsigned short apm_event_t; typedef unsigned short apm_eventinfo_t; struct apm_bios_info { __u16 version; __u16 cseg; __u32 offset; __u16 cseg_16; __u16 dseg; __u16 flags; __u16 cseg_len; __u16 cseg_16_len; __u16 dseg_len; }; /* * Power states */ #define APM_STATE_READY 0x0000 #define APM_STATE_STANDBY 0x0001 #define APM_STATE_SUSPEND 0x0002 #define APM_STATE_OFF 0x0003 #define APM_STATE_BUSY 0x0004 #define APM_STATE_REJECT 0x0005 #define APM_STATE_OEM_SYS 0x0020 #define APM_STATE_OEM_DEV 0x0040 #define APM_STATE_DISABLE 0x0000 #define APM_STATE_ENABLE 0x0001 #define APM_STATE_DISENGAGE 0x0000 #define APM_STATE_ENGAGE 0x0001 /* * Events (results of Get PM Event) */ #define APM_SYS_STANDBY 0x0001 #define APM_SYS_SUSPEND 0x0002 #define APM_NORMAL_RESUME 0x0003 #define APM_CRITICAL_RESUME 0x0004 #define APM_LOW_BATTERY 0x0005 #define APM_POWER_STATUS_CHANGE 0x0006 #define APM_UPDATE_TIME 0x0007 #define APM_CRITICAL_SUSPEND 0x0008 #define APM_USER_STANDBY 0x0009 #define APM_USER_SUSPEND 0x000a #define APM_STANDBY_RESUME 0x000b #define APM_CAPABILITY_CHANGE 0x000c /* * Error codes */ #define APM_SUCCESS 0x00 #define APM_DISABLED 0x01 #define APM_CONNECTED 0x02 #define APM_NOT_CONNECTED 0x03 #define APM_16_CONNECTED 0x05 #define APM_16_UNSUPPORTED 0x06 #define APM_32_CONNECTED 0x07 #define APM_32_UNSUPPORTED 0x08 #define APM_BAD_DEVICE 0x09 #define APM_BAD_PARAM 0x0a #define APM_NOT_ENGAGED 0x0b #define APM_BAD_FUNCTION 0x0c #define APM_RESUME_DISABLED 0x0d #define APM_NO_ERROR 0x53 #define APM_BAD_STATE 0x60 #define APM_NO_EVENTS 0x80 #define APM_NOT_PRESENT 0x86 /* * APM Device IDs */ #define APM_DEVICE_BIOS 0x0000 #define APM_DEVICE_ALL 0x0001 #define APM_DEVICE_DISPLAY 0x0100 #define APM_DEVICE_STORAGE 0x0200 #define APM_DEVICE_PARALLEL 0x0300 #define APM_DEVICE_SERIAL 0x0400 #define APM_DEVICE_NETWORK 0x0500 #define APM_DEVICE_PCMCIA 0x0600 #define APM_DEVICE_BATTERY 0x8000 #define APM_DEVICE_OEM 0xe000 #define APM_DEVICE_OLD_ALL 0xffff #define APM_DEVICE_CLASS 0x00ff #define APM_DEVICE_MASK 0xff00 /* * Battery status */ #define APM_MAX_BATTERIES 2 /* * APM defined capability bit flags */ #define APM_CAP_GLOBAL_STANDBY 0x0001 #define APM_CAP_GLOBAL_SUSPEND 0x0002 #define APM_CAP_RESUME_STANDBY_TIMER 0x0004 /* Timer resume from standby */ #define APM_CAP_RESUME_SUSPEND_TIMER 0x0008 /* Timer resume from suspend */ #define APM_CAP_RESUME_STANDBY_RING 0x0010 /* Resume on Ring fr standby */ #define APM_CAP_RESUME_SUSPEND_RING 0x0020 /* Resume on Ring fr suspend */ #define APM_CAP_RESUME_STANDBY_PCMCIA 0x0040 /* Resume on PCMCIA Ring */ #define APM_CAP_RESUME_SUSPEND_PCMCIA 0x0080 /* Resume on PCMCIA Ring */ /* * ioctl operations */ #include #define APM_IOC_STANDBY _IO('A', 1) #define APM_IOC_SUSPEND _IO('A', 2) #endif /* LINUX_APM_H */ /* * Copyright (C) 2005-2007 Jiri Slaby * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #ifndef __PHANTOM_H #define __PHANTOM_H #include /* PHN_(G/S)ET_REG param */ struct phm_reg { __u32 reg; __u32 value; }; /* PHN_(G/S)ET_REGS param */ struct phm_regs { __u32 count; __u32 mask; __u32 values[8]; }; #define PH_IOC_MAGIC 'p' #define PHN_GET_REG _IOWR(PH_IOC_MAGIC, 0, struct phm_reg *) #define PHN_SET_REG _IOW(PH_IOC_MAGIC, 1, struct phm_reg *) #define PHN_GET_REGS _IOWR(PH_IOC_MAGIC, 2, struct phm_regs *) #define PHN_SET_REGS _IOW(PH_IOC_MAGIC, 3, struct phm_regs *) /* this ioctl tells the driver, that the caller is not OpenHaptics and might * use improved registers update (no more phantom switchoffs when using * libphantom) */ #define PHN_NOT_OH _IO(PH_IOC_MAGIC, 4) #define PHN_GETREG _IOWR(PH_IOC_MAGIC, 5, struct phm_reg) #define PHN_SETREG _IOW(PH_IOC_MAGIC, 6, struct phm_reg) #define PHN_GETREGS _IOWR(PH_IOC_MAGIC, 7, struct phm_regs) #define PHN_SETREGS _IOW(PH_IOC_MAGIC, 8, struct phm_regs) #define PHN_CONTROL 0x6 /* control byte in iaddr space */ #define PHN_CTL_AMP 0x1 /* switch after torques change */ #define PHN_CTL_BUT 0x2 /* is button switched */ #define PHN_CTL_IRQ 0x10 /* is irq enabled */ #define PHN_ZERO_FORCE 2048 /* zero torque on motor */ #endif #ifndef _LINUX_MMAN_H #define _LINUX_MMAN_H #include #define MREMAP_MAYMOVE 1 #define MREMAP_FIXED 2 #define OVERCOMMIT_GUESS 0 #define OVERCOMMIT_ALWAYS 1 #define OVERCOMMIT_NEVER 2 #endif /* _LINUX_MMAN_H */ /*****************************************************************************/ /* * cdk.h -- CDK interface definitions. * * Copyright (C) 1996-1998 Stallion Technologies * Copyright (C) 1994-1996 Greg Ungerer. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /*****************************************************************************/ #ifndef _CDK_H #define _CDK_H /*****************************************************************************/ #pragma pack(2) /* * The following set of definitions is used to communicate with the * shared memory interface of the Stallion intelligent multiport serial * boards. The definitions in this file are taken directly from the * document titled "Generic Stackable Interface, Downloader and * Communications Development Kit". */ /* * Define the set of important shared memory addresses. These are * required to initialize the board and get things started. All of these * addresses are relative to the start of the shared memory. */ #define CDK_SIGADDR 0x200 #define CDK_FEATADDR 0x280 #define CDK_CDKADDR 0x300 #define CDK_RDYADDR 0x262 #define CDK_ALIVEMARKER 13 /* * On hardware power up the ROMs located on the EasyConnection 8/64 will * fill out the following signature information into shared memory. This * way the host system can quickly determine that the board is present * and is operational. */ typedef struct cdkecpsig { unsigned long magic; unsigned short romver; unsigned short cputype; unsigned char panelid[8]; } cdkecpsig_t; #define ECP_MAGIC 0x21504345 /* * On hardware power up the ROMs located on the ONboard, Stallion and * Brumbys will fill out the following signature information into shared * memory. This way the host system can quickly determine that the board * is present and is operational. */ typedef struct cdkonbsig { unsigned short magic0; unsigned short magic1; unsigned short magic2; unsigned short magic3; unsigned short romver; unsigned short memoff; unsigned short memseg; unsigned short amask0; unsigned short pic; unsigned short status; unsigned short btype; unsigned short clkticks; unsigned short clkspeed; unsigned short amask1; unsigned short amask2; } cdkonbsig_t; #define ONB_MAGIC0 0xf2a7 #define ONB_MAGIC1 0xa149 #define ONB_MAGIC2 0x6352 #define ONB_MAGIC3 0xf121 /* * Define the feature area structure. The feature area is the set of * startup parameters used by the slave image when it starts executing. * They allow for the specification of buffer sizes, debug trace, etc. */ typedef struct cdkfeature { unsigned long debug; unsigned long banner; unsigned long etype; unsigned long nrdevs; unsigned long brdspec; unsigned long txrqsize; unsigned long rxrqsize; unsigned long flags; } cdkfeature_t; #define ETYP_DDK 0 #define ETYP_CDK 1 /* * Define the CDK header structure. This is the info that the slave * environment sets up after it has been downloaded and started. It * essentially provides a memory map for the shared memory interface. */ typedef struct cdkhdr { unsigned short command; unsigned short status; unsigned short port; unsigned short mode; unsigned long cmd_buf[14]; unsigned short alive_cnt; unsigned short intrpt_mode; unsigned char intrpt_id[8]; unsigned char ver_release; unsigned char ver_modification; unsigned char ver_fix; unsigned char deadman_restart; unsigned short deadman; unsigned short nrdevs; unsigned long memp; unsigned long hostp; unsigned long slavep; unsigned char hostreq; unsigned char slavereq; unsigned char cmd_reserved[30]; } cdkhdr_t; #define MODE_DDK 0 #define MODE_CDK 1 #define IMD_INTR 0x0 #define IMD_PPINTR 0x1 #define IMD_POLL 0xff /* * Define the memory mapping structure. This structure is pointed to by * the memp field in the stlcdkhdr struct. As many as these structures * as required are layed out in shared memory to define how the rest of * shared memory is divided up. There will be one for each port. */ typedef struct cdkmem { unsigned short dtype; unsigned long offset; } cdkmem_t; #define TYP_UNDEFINED 0x0 #define TYP_ASYNCTRL 0x1 #define TYP_ASYNC 0x20 #define TYP_PARALLEL 0x40 #define TYP_SYNCX21 0x60 /*****************************************************************************/ /* * Following is a set of defines and structures used to actually deal * with the serial ports on the board. Firstly is the set of commands * that can be applied to ports. */ #define ASYCMD (((unsigned long) 'a') << 8) #define A_NULL (ASYCMD | 0) #define A_FLUSH (ASYCMD | 1) #define A_BREAK (ASYCMD | 2) #define A_GETPORT (ASYCMD | 3) #define A_SETPORT (ASYCMD | 4) #define A_SETPORTF (ASYCMD | 5) #define A_SETPORTFTX (ASYCMD | 6) #define A_SETPORTFRX (ASYCMD | 7) #define A_GETSIGNALS (ASYCMD | 8) #define A_SETSIGNALS (ASYCMD | 9) #define A_SETSIGNALSF (ASYCMD | 10) #define A_SETSIGNALSFTX (ASYCMD | 11) #define A_SETSIGNALSFRX (ASYCMD | 12) #define A_GETNOTIFY (ASYCMD | 13) #define A_SETNOTIFY (ASYCMD | 14) #define A_NOTIFY (ASYCMD | 15) #define A_PORTCTRL (ASYCMD | 16) #define A_GETSTATS (ASYCMD | 17) #define A_RQSTATE (ASYCMD | 18) #define A_FLOWSTATE (ASYCMD | 19) #define A_CLEARSTATS (ASYCMD | 20) /* * Define those arguments used for simple commands. */ #define FLUSHRX 0x1 #define FLUSHTX 0x2 #define BREAKON -1 #define BREAKOFF -2 /* * Define the port setting structure, and all those defines that go along * with it. Basically this structure defines the characteristics of this * port: baud rate, chars, parity, input/output char cooking etc. */ typedef struct asyport { unsigned long baudout; unsigned long baudin; unsigned long iflag; unsigned long oflag; unsigned long lflag; unsigned long pflag; unsigned long flow; unsigned long spare1; unsigned short vtime; unsigned short vmin; unsigned short txlo; unsigned short txhi; unsigned short rxlo; unsigned short rxhi; unsigned short rxhog; unsigned short spare2; unsigned char csize; unsigned char stopbs; unsigned char parity; unsigned char stopin; unsigned char startin; unsigned char stopout; unsigned char startout; unsigned char parmark; unsigned char brkmark; unsigned char cc[11]; } asyport_t; #define PT_STOP1 0x0 #define PT_STOP15 0x1 #define PT_STOP2 0x2 #define PT_NOPARITY 0x0 #define PT_ODDPARITY 0x1 #define PT_EVENPARITY 0x2 #define PT_MARKPARITY 0x3 #define PT_SPACEPARITY 0x4 #define F_NONE 0x0 #define F_IXON 0x1 #define F_IXOFF 0x2 #define F_IXANY 0x4 #define F_IOXANY 0x8 #define F_RTSFLOW 0x10 #define F_CTSFLOW 0x20 #define F_DTRFLOW 0x40 #define F_DCDFLOW 0x80 #define F_DSROFLOW 0x100 #define F_DSRIFLOW 0x200 #define FI_NORX 0x1 #define FI_RAW 0x2 #define FI_ISTRIP 0x4 #define FI_UCLC 0x8 #define FI_INLCR 0x10 #define FI_ICRNL 0x20 #define FI_IGNCR 0x40 #define FI_IGNBREAK 0x80 #define FI_DSCRDBREAK 0x100 #define FI_1MARKBREAK 0x200 #define FI_2MARKBREAK 0x400 #define FI_XCHNGBREAK 0x800 #define FI_IGNRXERRS 0x1000 #define FI_DSCDRXERRS 0x2000 #define FI_1MARKRXERRS 0x4000 #define FI_2MARKRXERRS 0x8000 #define FI_XCHNGRXERRS 0x10000 #define FI_DSCRDNULL 0x20000 #define FO_OLCUC 0x1 #define FO_ONLCR 0x2 #define FO_OOCRNL 0x4 #define FO_ONOCR 0x8 #define FO_ONLRET 0x10 #define FO_ONL 0x20 #define FO_OBS 0x40 #define FO_OVT 0x80 #define FO_OFF 0x100 #define FO_OTAB1 0x200 #define FO_OTAB2 0x400 #define FO_OTAB3 0x800 #define FO_OCR1 0x1000 #define FO_OCR2 0x2000 #define FO_OCR3 0x4000 #define FO_OFILL 0x8000 #define FO_ODELL 0x10000 #define P_RTSLOCK 0x1 #define P_CTSLOCK 0x2 #define P_MAPRTS 0x4 #define P_MAPCTS 0x8 #define P_LOOPBACK 0x10 #define P_DTRFOLLOW 0x20 #define P_FAKEDCD 0x40 #define P_RXIMIN 0x10000 #define P_RXITIME 0x20000 #define P_RXTHOLD 0x40000 /* * Define a structure to communicate serial port signal and data state * information. */ typedef struct asysigs { unsigned long data; unsigned long signal; unsigned long sigvalue; } asysigs_t; #define DT_TXBUSY 0x1 #define DT_TXEMPTY 0x2 #define DT_TXLOW 0x4 #define DT_TXHIGH 0x8 #define DT_TXFULL 0x10 #define DT_TXHOG 0x20 #define DT_TXFLOWED 0x40 #define DT_TXBREAK 0x80 #define DT_RXBUSY 0x100 #define DT_RXEMPTY 0x200 #define DT_RXLOW 0x400 #define DT_RXHIGH 0x800 #define DT_RXFULL 0x1000 #define DT_RXHOG 0x2000 #define DT_RXFLOWED 0x4000 #define DT_RXBREAK 0x8000 #define SG_DTR 0x1 #define SG_DCD 0x2 #define SG_RTS 0x4 #define SG_CTS 0x8 #define SG_DSR 0x10 #define SG_RI 0x20 /* * Define the notification setting structure. This is used to tell the * port what events we want to be informed about. Fields here use the * same defines as for the asysigs structure above. */ typedef struct asynotify { unsigned long ctrl; unsigned long data; unsigned long signal; unsigned long sigvalue; } asynotify_t; /* * Define the port control structure. It is used to do fine grain * control operations on the port. */ typedef struct { unsigned long rxctrl; unsigned long txctrl; char rximdch; char tximdch; char spare1; char spare2; } asyctrl_t; #define CT_ENABLE 0x1 #define CT_DISABLE 0x2 #define CT_STOP 0x4 #define CT_START 0x8 #define CT_STARTFLOW 0x10 #define CT_STOPFLOW 0x20 #define CT_SENDCHR 0x40 /* * Define the stats structure kept for each port. This is a useful set * of data collected for each port on the slave. The A_GETSTATS command * is used to retrieve this data from the slave. */ typedef struct asystats { unsigned long opens; unsigned long txchars; unsigned long rxchars; unsigned long txringq; unsigned long rxringq; unsigned long txmsgs; unsigned long rxmsgs; unsigned long txflushes; unsigned long rxflushes; unsigned long overruns; unsigned long framing; unsigned long parity; unsigned long ringover; unsigned long lost; unsigned long rxstart; unsigned long rxstop; unsigned long txstart; unsigned long txstop; unsigned long dcdcnt; unsigned long dtrcnt; unsigned long ctscnt; unsigned long rtscnt; unsigned long dsrcnt; unsigned long ricnt; unsigned long txbreaks; unsigned long rxbreaks; unsigned long signals; unsigned long state; unsigned long hwid; } asystats_t; /*****************************************************************************/ /* * All command and control communication with a device on the slave is * via a control block in shared memory. Each device has its own control * block, defined by the following structure. The control block allows * the host to open, close and control the device on the slave. */ typedef struct cdkctrl { unsigned char open; unsigned char close; unsigned long openarg; unsigned long closearg; unsigned long cmd; unsigned long status; unsig