XOFFSET_4 46 /* tex4/1 */ #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ #define R200_EMIT_PP_CUBIC_FACES_0 61 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 #define R200_EMIT_PP_CUBIC_FACES_1 63 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 #define R200_EMIT_PP_CUBIC_FACES_2 65 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 #define R200_EMIT_PP_CUBIC_FACES_3 67 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 #define R200_EMIT_PP_CUBIC_FACES_4 69 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 #define R200_EMIT_PP_CUBIC_FACES_5 71 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 #define RADEON_EMIT_PP_TEX_SIZE_0 73 #define RADEON_EMIT_PP_TEX_SIZE_1 74 #define RADEON_EMIT_PP_TEX_SIZE_2 75 #define R200_EMIT_RB3D_BLENDCOLOR 76 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 #define RADEON_EMIT_PP_CUBIC_FACES_0 78 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 #define RADEON_EMIT_PP_CUBIC_FACES_1 80 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 #define RADEON_EMIT_PP_CUBIC_FACES_2 82 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 #define R200_EMIT_PP_TRI_PERF_CNTL 84 #define R200_EMIT_PP_AFS_0 85 #define R200_EMIT_PP_AFS_1 86 #define R200_EMIT_ATF_TFACTOR 87 #define R200_EMIT_PP_TXCTLALL_0 88 #define R200_EMIT_PP_TXCTLALL_1 89 #define R200_EMIT_PP_TXCTLALL_2 90 #define R200_EMIT_PP_TXCTLALL_3 91 #define R200_EMIT_PP_TXCTLALL_4 92 #define R200_EMIT_PP_TXCTLALL_5 93 #define R200_EMIT_VAP_PVS_CNTL 94 #define RADEON_MAX_STATE_PACKETS 95 /* Commands understood by cmd_buffer ioctl. More can be added but * obviously these can't be removed or changed: */ #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ #define RADEON_CMD_SCALARS 2 /* emit scalar data */ #define RADEON_CMD_VECTORS 3 /* emit vector data */ #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ #define RADEON_CMD_PACKET3 5 /* emit hw packet */ #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: * doesn't make the cpu wait, just * the graphics hardware */ #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ typedef union { int i; struct { unsigned char cmd_type, pad0, pad1, pad2; } header; struct { unsigned char cmd_type, packet_id, pad0, pad1; } packet; struct { unsigned char cmd_type, offset, stride, count; } scalars; struct { unsigned char cmd_type, offset, stride, count; } vectors; struct { unsigned char cmd_type, addr_lo, addr_hi, count; } veclinear; struct { unsigned char cmd_type, buf_idx, pad0, pad1; } dma; struct { unsigned char cmd_type, flags, pad0, pad1; } wait; } drm_radeon_cmd_header_t; #define RADEON_WAIT_2D 0x1 #define RADEON_WAIT_3D 0x2 /* Allowed parameters for R300_CMD_PACKET3 */ #define R300_CMD_PACKET3_CLEAR 0 #define R300_CMD_PACKET3_RAW 1 /* Commands understood by cmd_buffer ioctl for R300. * The interface has not been stabilized, so some of these may be removed * and eventually reordered before stabilization. */ #define R300_CMD_PACKET0 1 #define R300_CMD_VPU 2 /* emit vertex program upload */ #define R300_CMD_PACKET3 3 /* emit a packet3 */ #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ #define R300_CMD_CP_DELAY 5 #define R300_CMD_DMA_DISCARD 6 #define R300_CMD_WAIT 7 # define R300_WAIT_2D 0x1 # define R300_WAIT_3D 0x2 /* these two defines are DOING IT WRONG - however * we have userspace which relies on using these. * The wait interface is backwards compat new * code should use the NEW_WAIT defines below * THESE ARE NOT BIT FIELDS */ # define R300_WAIT_2D_CLEAN 0x3 # define R300_WAIT_3D_CLEAN 0x4 # define R300_NEW_WAIT_2D_3D 0x3 # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 #define R300_CMD_SCRATCH 8 #define R300_CMD_R500FP 9 typedef union { unsigned int u; struct { unsigned char cmd_type, pad0, pad1, pad2; } header; struct { unsigned char cmd_type, count, reglo, reghi; } packet0; struct { unsigned char cmd_type, count, adrlo, adrhi; } vpu; struct { unsigned char cmd_type, packet, pad0, pad1; } packet3; struct { unsigned char cmd_type, packet; unsigned short count; /* amount of packet2 to emit */ } delay; struct { unsigned char cmd_type, buf_idx, pad0, pad1; } dma; struct { unsigned char cmd_type, flags, pad0, pad1; } wait; struct { unsigned char cmd_type, reg, n_bufs, flags; } scratch; struct { unsigned char cmd_type, count, adrlo, adrhi_flags; } r500fp; } drm_r300_cmd_header_t; #define RADG¹H¹I¹J¹K¹L¹M¹N¹O¹P¹Q¹R¹S¹T¹U¹V¹W¹X¹Y¹Z¹EON_FRONT 0x1 #define RADEON_BACK 0x2 #define RADEON_DEPTH 0x4 #define RADEON_STENCIL 0x8 #define RADEON_CLEAR_FASTZ 0x80000000 #define RADEON_USE_HIERZ 0x40000000 #define RADEON_USE_COMP_ZBUF 0x20000000 #define R500FP_CONSTANT_TYPE (1 << 1) #define R500FP_CONSTANT_CLAMP (1 << 2) /* Primitive types */ #define RADEON_POINTS 0x1 #define RADEON_LINES 0x2 #define RADEON_LINE_STRIP 0x3 #define RADEON_TRIANGLES 0x4 #define RADEON_TRIANGLE_FAN 0x5 #define RADEON_TRIANGLE_STRIP 0x6 /* Vertex/indirect buffer size */ #define RADEON_BUFFER_SIZE 65536 /* Byte offsets for indirect buffer data */ #define RADEON_INDEX_PRIM_OFFSET 20 #define RADEON_SCRATCH_REG_OFFSET 32 #define R600_SCRATCH_REG_OFFSET 256 #define RADEON_NR_SAREA_CLIPRECTS 12 /* There are 2 heaps (local/GART). Each region within a heap is a * minimum of 64k, and there are at most 64 of them per heap. */ #define RADEON_LOCAL_TEX_HEAP 0 #define RADEON_GART_TEX_HEAP 1 #define RADEON_NR_TEX_HEAPS 2 #define RADEON_NR_TEX_REGIONS 64 #define RADEON_LOG_TEX_GRANULARITY 16 #define RADEON_MAX_TEXTURE_LEVELS 12 #define RADEON_MAX_TEXTURE_UNITS 3 #define RADEON_MAX_SURFACES 8 /* Blits have strict offset rules. All blit offset must be aligned on * a 1K-byte boundary. */ #define RADEON_OFFSET_SHIFT 10 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) #endif /* __RADEON_SAREA_DEFINES__ */ typedef struct { unsigned int red; unsigned int green; unsigned int blue; unsigned int alpha; } radeon_color_regs_t; typedef struct { /* Context state */ unsigned int pp_misc; /* 0x1c14 */ unsigned int pp_fog_color; unsigned int re_solid_color; unsigned int rb3d_blendcntl; unsigned int rb3d_depthoffset; unsigned int rb3d_depthpitch; unsigned int rb3d_zstencilcntl; unsigned int pp_cntl; /* 0x1c38 */ unsigned int rb3d_cntl; unsigned int rb3d_coloroffset; unsigned int re_width_height; unsigned int rb3d_colorpitch; unsigned int se_cntl; /* Vertex format state */ unsigned int se_coord_fmt; /* 0x1c50 */ /* Line state */ unsigned int re_line_pattern; /* 0x1cd0 */ unsigned int re_line_state; unsigned int se_line_width; /* 0x1db8 */ /* Bumpmap state */ unsigned int pp_lum_matrix; /* 0x1d00 */ unsigned int pp_rot_matrix_0; /* 0x1d58 */ unsigned int pp_rot_matrix_1; /* Mask state */ unsigned int rb3d_stencilrefmask; /* 0x1d7c */ unsigned int rb3d_ropcntl; unsigned int rb3d_planemask; /* Viewport state */ unsigned int se_vport_xscale; /* 0x1d98 */ unsigned int se_vport_xoffset; unsigned int se_vport_yscale; unsigned int se_vport_yoffset; unsigned int se_vport_zscale; unsigned int se_vport_zoffset; /* Setup state */ unsigned int se_cntl_status; /* 0x2140 */ /* Misc state */ unsigned int re_top_left; /* 0x26c0 */ unsigned int re_misc; } drm_radeon_context_regs_t; typedef struct { /* Zbias state */ unsigned int se_zbias_factor; /* 0x1dac */ unsigned int se_zbias_constant; } drm_radeon_context2_regs_t; /* Setup registers for each texture unit */ typedef struct { unsigned int pp_txfilter; unsigned int pp_txformat; unsigned int pp_txoffset; unsigned int pp_txcblend; unsigned int pp_txablend; unsigned int pp_tfactor; unsigned int pp_border_color; } drm_radeon_texture_regs_t; typedef struct { unsigned int start; unsigned int finish; unsigned int prim:8; unsigned int stateidx:8; unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ unsigned int vc_format; /* vertex format */ } drm_radeon_prim_t; typedef struct { drm_radeon_context_regs_t context; drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; drm_radeon_context2_regs_t context2; unsigned int dirty; } drm_radeon_state_t; typedef struct { /* The channel for communication of state information to the * kernel on firing a vertex buffer with either of the * obsoleted vertex/index ioctls. */ drm_radeon_context_regs_t context_state; drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; unsigned int dirty; unsigned int vertsize; unsigned int vc_format; /* The current cliprects, or a subset thereof. */ struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. */ unsigned int last_frame; unsigned int last_dispatch; unsigned int last_clear; struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; unsigned int tex_age[RADEON_NR_TEX_HEAPS]; int ctx_owner; int pfState; /* number of 3d windows (0,1,2ormore) */ int pfCurrentPage; /* which buffer is being displayed? */ int crtc2_base; /* CRTC2 frame offset */ int tiling_enabled; /* set by drm, read by 2d + 3d clients */ } drm_radeon_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmRadeon.h) * * KW: actually it's illegal to change any of this (backwards compatibility). */ /* Radeon specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_RADEON_CP_INIT 0x00 #define DRM_RADEON_CP_START 0x01 #define DRM_RADEON_CP_STOP 0x02 #define DRM_RADEON_CP_RESET 0x03 #define DRM_RADEON_CP_IDLE 0x04 #define DRM_RADEON_RESET 0x05 #define DRM_RADEON_FULLSCREEN 0x06 #define DRM_RADEON_SWAP 0x07 #define DRM_RADEON_CLEAR 0x08 #define DRM_RADEON_VERTEX 0x09 #define DRM_RADEON_INDICES 0x0A #define DRM_RADEON_NOT_USED #define DRM_RADEON_STIPPLE 0x0C #define DRM_RADEON_INDIRECT 0x0D #define DRM_RADEON_TEXTURE 0x0E #define DRM_RADEON_VERTEX2 0x0F #define DRM_RADEON_CMDBUF 0x10 #define DRM_RADEON_GETPARAM 0x11 #define DRM_RADEON_FLIP 0x12 #define DRM_RADEON_ALLOC 0x13 #define DRM_RADEON_FREE 0x14 #define DRM_RADEON_INIT_HEAP 0x15 #define DRM_RADEON_IRQ_EMIT 0x16 #define DRM_RADEON_IRQ_WAIT 0x17 #define DRM_RADEON_CP_RESUME 0x18 #define DRM_RADEON_SETPARAM 0x19 #define DRM_RADEON_SURF_ALLOC 0x1a #define DRM_RADEON_SURF_FREE 0x1b /* KMS ioctl */ #define DRM_RADEON_GEM_INFO 0x1c #define DRM_RADEON_GEM_CREATE 0x1d #define DRM_RADEON_GEM_MMAP 0x1e #define DRM_RADEON_GEM_PREAD 0x21 #define DRM_RADEON_GEM_PWRITE 0x22 #define DRM_RADEON_GEM_SET_DOMAIN 0x23 #define DRM_RADEON_GEM_WAIT_IDLE 0x24 #define DRM_RADEON_CS 0x26 #define DRM_RADEON_INFO 0x27 #define DRM_RADEON_GEM_SET_TILING 0x28 #define DRM_RADEON_GEM_GET_TILING 0x29 #define DRM_RADEON_GEM_BUSY 0x2a #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) /* KMS */ #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) typedef struct drm_radeon_init { enum { RADEON_INIT_CP = 0x01, RADEON_CLEANUP_CP = 0x02, RADEON_INIT_R200_CP = 0x03, RADEON_INIT_R300_CP = 0x04, RADEON_INIT_R600_CP = 0x05 } func; unsigned long sarea_priv_offset; int is_pci; int cp_mode; int gart_size; int ring_size; int usec_timeout; unsigned int fb_bpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; unsigned long ring_rptr_offset; unsigned long buffers_offset; unsigned long gart_textures_offset; } drm_radeon_init_t; typedef struct drm_radeon_cp_stop { int flush; int idle; } drm_radeon_cp_stop_t; typedef struct drm_radeon_fullscreen { enum { RADEON_INIT_FULLSCREEN = 0x01, RADEON_CLEANUP_FULLSCREEN = 0x02 } func; } drm_radeon_fullscreen_t; #define CLEAR_X1 0 #define CLEAR_Y1 1 #define CLEAR_X2 2 #define CLEAR_Y2 3 #define CLEAR_DEPTH 4 typedef union drm_radeon_clear_rect { float f[5]; unsigned int ui[5]; } drm_radeon_clear_rect_t; typedef struct drm_radeon_clear { unsigned int flags; unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; unsigned int depth_mask; /* misnamed field: should be stencil */ drm_radeon_clear_rect_t *depth_boxes; } drm_radeon_clear_t; typedef struct drm_radeon_vertex { int prim; int idx; /* Index of vertex buffer */ int count; /* Number of vertices in buffer */ int discard; /* Client finished with buffer? */ } drm_radeon_vertex_t; typedef struct drm_radeon_indices { int prim; int idx; int start; int end; int discard; /* Client finished with buffer? */ } drm_radeon_indices_t; /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices * - allows multiple primitives and state changes in a single ioctl * - supports driver change to emit native primitives */ typedef struct drm_radeon_vertex2 { int idx; /* Index of vertex buffer */ int discard; /* Client finished with buffer? */ int nr_states; drm_radeon_state_t *state; int nr_prims; drm_radeon_prim_t *prim; } drm_radeon_vertex2_t; /* v1.3 - obsoletes drm_radeon_vertex2 * - allows arbitarily large cliprect list * - allows updating of tcl packet, vector and scalar state * - allows memory-efficient description of state updates * - allows state to be emitted without a primitive * (for clears, ctx switches) * - allows more than one dma buffer to be referenced per ioctl * - supports tcl driver * - may be extended in future versions with new cmd types, packets */ typedef struct drm_radeon_cmd_buffer { int bufsz; char *buf; int nbox; struct drm_clip_rect *boxes; } drm_radeon_cmd_buffer_t; typedef struct drm_radeon_tex_image { unsigned int x, y; /* Blit coordinates */ unsigned int width, height; const void *data; } drm_radeon_tex_image_t; typedef struct drm_radeon_texture { unsigned int offset; int pitch; int format; int width; /* Texture image coordinates */ int height; drm_radeon_tex_image_t *image; } drm_radeon_texture_t; typedef struct drm_radeon_stipple { unsigned int *mask; } drm_radeon_stipple_t; typedef struct drm_radeon_indirect { int idx; int start; int end; int discard; } drm_radeon_indirect_t; /* enum for card type parameters */ #define RADEON_CARD_PCI 0 #define RADEON_CARD_AGP 1 #define RADEON_CARD_PCIE 2 /* 1.3: An ioctl to get parameters that aren't available to the 3d * client any other way. */ #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ #define RADEON_PARAM_LAST_FRAME 2 #define RADEON_PARAM_LAST_DISPATCH 3 #define RADEON_PARAM_LAST_CLEAR 4 /* Added with DRM version 1.6. */ #define RADEON_PARAM_IRQ_NR 5 #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ /* Added with DRM version 1.8. */ #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ #define RADEON_PARAM_STATUS_HANDLE 8 #define RADEON_PARAM_SAREA_HANDLE 9 #define RADEON_PARAM_GART_TEX_HANDLE 10 #define RADEON_PARAM_SCRATCH_OFFSET 11 #define RADEON_PARAM_CARD_TYPE 12 #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ #define RADEON_PARAM_DEVICE_ID 16 #define RADEON_PARAM_NUM_Z_PIPES 17 /* num Z pipes */ typedef struct drm_radeon_getparam { int param; void *value; } drm_radeon_getparam_t; /* 1.6: Set up a memory manager for regions of shared memory: */ #define RADEON_MEM_REGION_GART 1 #define RADEON_MEM_REGION_FB 2 typedef struct drm_radeon_mem_alloc { int region; int alignment; int size; int *region_offset; /* offset from start of fb or GART */ } drm_radeon_mem_alloc_t; typedef struct drm_radeon_mem_free { int region; int region_offset; } drm_radeon_mem_free_t; typedef struct drm_radeon_mem_init_heap { int region; int size; int start; } drm_radeon_mem_init_heap_t; /* 1.6: Userspace can request & wait on irq's: */ typedef struct drm_radeon_irq_emit { int *irq_seq; } drm_radeon_irq_emit_t; typedef struct drm_radeon_irq_wait { int irq_seq; } drm_radeon_irq_wait_t; /* 1.10: Clients tell the DRM where they think the framebuffer is located in * the card's address space, via a new generic ioctl to set parameters */ typedef struct drm_radeon_setparam { unsigned int param; __s64 value; } drm_radeon_setparam_t; #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ /* 1.14: Clients can allocate/free a surface */ typedef struct drm_radeon_surface_alloc { unsigned int address; unsigned int size; unsigned int flags; } drm_radeon_surface_alloc_t; typedef struct drm_radeon_surface_free { unsigned int address; } drm_radeon_surface_free_t; #define DRM_RADEON_VBLANK_CRTC1 1 #define DRM_RADEON_VBLANK_CRTC2 2 /* * Kernel modesetting world below. */ #define RADEON_GEM_DOMAIN_CPU 0x1 #define RADEON_GEM_DOMAIN_GTT 0x2 #define RADEON_GEM_DOMAIN_VRAM 0x4 struct drm_radeon_gem_info { uint64_t gart_size; uint64_t vram_size; uint64_t vram_visible; }; #define RADEON_GEM_NO_BACKING_STORE 1 struct drm_radeon_gem_create { uint64_t size; uint64_t alignment; uint32_t handle; uint32_t initial_domain; uint32_t flags; }; #define RADEON_TILING_MACRO 0x1 #define RADEON_TILING_MICRO 0x2 #define RADEON_TILING_SWAP_16BIT 0x4 #define RADEON_TILING_SWAP_32BIT 0x8 #define RADEON_TILING_SURFACE 0x10 /* this object requires a surface * when mapped - i.e. front buffer */ #define RADEON_TILING_MICRO_SQUARE 0x20 struct drm_radeon_gem_set_tiling { uint32_t handle; uint32_t tiling_flags; uint32_t pitch; }; struct drm_radeon_gem_get_tiling { uint32_t handle; uint32_t tiling_flags; uint32_t pitch; }; struct drm_radeon_gem_mmap { uint32_t handle; uint32_t pad; uint64_t offset; uint64_t size; uint64_t addr_ptr; }; struct drm_radeon_gem_set_domain { uint32_t handle; uint32_t read_domains; uint32_t write_domain; }; struct drm_radeon_gem_wait_idle { uint32_t handle; uint32_t pad; }; struct drm_radeon_gem_busy { uint32_t handle; uint32_t domain; }; struct drm_radeon_gem_pread { /** Handle for the object being read. */ uint32_t handle; uint32_t pad; /** Offset into the object to read from */ uint64_t offset; /** Length of data to read */ uint64_t size; /** Pointer to write the data into. */ /* void *, but pointers are not 32/64 compatible */ uint64_t data_ptr; }; struct drm_radeon_gem_pwrite { /** Handle for the object being written to. */ uint32_t handle; uint32_t pad; /** Offset into the object to write to */ uint64_t offset; /** Length of data to write */ uint64_t size; /** Pointer to read the data from. */ /* void *, but pointers are not 32/64 compatible */ uint64_t data_ptr; }; #define RADEON_CHUNK_ID_RELOCS 0x01 #define RADEON_CHUNK_ID_IB 0x02 struct drm_radeon_cs_chunk { uint32_t chunk_id; uint32_t length_dw; uint64_t chunk_data; }; struct drm_radeon_cs_reloc { uint32_t handle; uint32_t read_domains; uint32_t write_domain; uint32_t flags; }; struct drm_radeon_cs { uint32_t num_chunks; uint32_t cs_id; /* this points to uint64_t * which point to cs chunks */ uint64_t chunks; /* updates to the limits after this CS ioctl */ uint64_t gart_limit; uint64_t vram_limit; }; #define RADEON_INFO_DEVICE_ID 0x00 #define RADEON_INFO_NUM_GB_PIPES 0x01 #define RADEON_INFO_NUM_Z_PIPES 0x02 #define RADEON_INFO_ACCEL_WORKING 0x03 #define RADEON_INFO_CRTC_FROM_ID 0x04 #define RADEON_INFO_ACCEL_WORKING2 0x05 #define RADEON_INFO_TILING_CONFIG 0x06 #define RADEON_INFO_WANT_HYPERZ 0x07 struct drm_radeon_info { uint32_t request; uint32_t pad; uint64_t value; }; #endif cmd_/usr/local/home/bellard/cpux86/rootdisk/buildroot-2011.02/output/toolchain/linux/include/drm/.install := perl scripts/headers_install.pl /usr/local/home/bellard/cpux86/rootdisk/buildroot-2011.02/output/toolchain/linux-2.6.37.2/include/drm /usr/local/home/bellard/cpux86/rootdisk/buildroot-2011.02/output/toolchain/linux/include/drm x86 drm.h drm_mode.h drm_sarea.h i810_drm.h i830_drm.h i915_drm.h mga_drm.h nouveau_drm.h r128_drm.h radeon_drm.h savage_drm.h sis_drm.h via_drm.h vmwgfx_drm.h; perl scripts/headers_install.pl /usr/local/home/bellard/cpux86/rootdisk/buildroot-2011.02/output/toolchain/linux-2.6.37.2/include/drm /usr/local/home/bellard/cpux86/rootdisk/buildroot-2011.02/output/toolchain/linux/include/drm x86 ; touch /usr/local/home/bellard/cpux86/rootdisk/buildroot-2011.02/output/toolchain/linux/include/drm/.install /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com */ /* * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. * All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. * * Authors: * Gareth Hughes * Kevin E. Martin */ #ifndef __R128_DRM_H__ #define __R128_DRM_H__ /* WARNING: If you change any of these defines, make sure to change the * defines in the X server file (r128_sarea.h) */ #ifndef __R128_SAREA_DEFINES__ #define __R128_SAREA_DEFINES__ /* What needs to be changed for the current vertex buffer? */ #define R128_UPLOAD_CONTEXT 0x001 #define R128_UPLOAD_SETUP 0x002 #define R128_UPLOAD_TEX0 0x004 #define R128_UPLOAD_TEX1 0x008 #define R128_UPLOAD_TEX0IMAGES 0x010 #define R128_UPLOAD_TEX1IMAGES 0x020 #define R128_UPLOAD_CORE 0x040 #define R128_UPLOAD_MASKS 0x080 #define R128_UPLOAD_WINDOW 0x100 #define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ #define R128_REQUIRE_QUIESCENCE 0x400 #define R128_UPLOAD_ALL 0x7ff #define R128_FRONT 0x1 #define R128_BACK 0x2 #define R128_DEPTH 0x4 /* Primitive types */ #define R128_POINTS 0x1 #define R128_LINES 0x2 #define R128_LINE_STRIP 0x3 #define R128_TRIANGLES 0x4 #define R128_TRIANGLE_FAN 0x5 #define R128_TRIANGLE_STRIP 0x6 /* Vertex/indirect buffer size */ #define R128_BUFFER_SIZE 16384 /* Byte offsets for indirect buffer data */ #define R128_INDEX_PRIM_OFFSET 20 #define R128_HOSTDATA_BLIT_OFFSET 32 /* Keep these small for testing. */ #define R128_NR_SAREA_CLIPRECTS 12 /* There are 2 heaps (local/AGP). Each region within a heap is a * minimum of 64k, and there are at most 64 of them per heap. */ #define R128_LOCAL_TEX_HEAP 0 #define R128_AGP_TEX_HEAP 1 #define R128_NR_TEX_HEAPS 2 #define R128_NR_TEX_REGIONS 64 #define R128_LOG_TEX_GRANULARITY 16 #define R128_NR_CONTEXT_REGS 12 #define R128_MAX_TEXTURE_LEVELS 11 #define R128_MAX_TEXTURE_UNITS 2 #endif /* __R128_SAREA_DEFINES__ */ typedef struct { /* Context state - can be written in one large chunk */ unsigned int dst_pitch_offset_c; unsigned int dp_gui_master_cntl_c; unsigned int sc_top_left_c; unsigned int sc_bottom_right_c; unsigned int z_offset_c; unsigned int z_pitch_c; unsigned int z_sten_cntl_c; unsigned int tex_cntl_c; unsigned int misc_3d_state_cntl_reg; unsigned int texture_clr_cmp_clr_c; unsigned int texture_clr_cmp_msk_c; unsigned int fog_color_c; /* Texture state */ unsigned int tex_size_pitch_c; unsigned int constant_color_c; /* Setup state */ unsigned int pm4_vc_fpu_setup; unsigned int setup_cntl; /* Mask state */ unsigned int dp_write_mask; unsigned int sten_ref_mask_c; unsigned int plane_3d_mask_c; /* Window state */ unsigned int window_xy_offset; /* Core state */ unsigned int scale_3d_cntl; } drm_r128_context_regs_t; /* Setup registers for each texture unit */ typedef struct { unsigned int tex_cntl; unsigned int tex_combine_cntl; unsigned int tex_size_pitch; unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; unsigned int tex_border_color; } drm_r128_texture_regs_t; typedef struct drm_r128_sarea { /* The channel for communication of state information to the kernel * on firing a vertex buffer. */ drm_r128_context_regs_t context_state; drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; unsigned int dirty; unsigned int vertsize; unsigned int vc_format; /* The current cliprects, or a subset thereof. */ struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; unsigned int nbox; /* Counters for client-side throttling of rendering clients. */ unsigned int last_frame; unsigned int last_dispatch; struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; unsigned int tex_age[R128_NR_TEX_HEAPS]; int ctx_owner; int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ int pfCurrentPage; /* which buffer is being displayed? */ } drm_r128_sarea_t; /* WARNING: If you change any of these defines, make sure to change the * defines in the Xserver file (xf86drmR128.h) */ /* Rage 128 specific ioctls * The device specific ioctl range is 0x40 to 0x79. */ #define DRM_R128_INIT 0x00 #define DRM_R128_CCE_START 0x01 #define DRM_R128_CCE_STOP 0x02 #define DRM_R128_CCE_RESET 0x03 #define DRM_R128_CCE_IDLE 0x04 /* 0x05 not used */ #define DRM_R128_RESET 0x06 #define DRM_R128_SWAP 0x07 #define DRM_R128_CLEAR 0x08 #define DRM_R128_VERTEX 0x09 #define DRM_R128_INDICES 0x0a #define DRM_R128_BLIT 0x0b #define DRM_R128_DEPTH 0x0c #define DRM_R128_STIPPLE 0x0d /* 0x0e not used */ #define DRM_R128_INDIRECT 0x0f #define DRM_R128_FULLSCREEN 0x10 #define DRM_R128_CLEAR2 0x11 #define DRM_R128_GETPARAM 0x12 #define DRM_R128_FLIP 0x13 #define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) #define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) #define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) #define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) #define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) /* 0x05 not used */ #define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) #define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) #define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) #define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) #define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) #define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) #define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) #define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) /* 0x0e not used */ #define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) #define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) #define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) #define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) typedef struct drm_r128_init { enum { R128_INIT_CCE = 0x01, R128_CLEANUP_CCE = 0x02 } func; unsigned long sarea_priv_offset; int is_pci; int cce_mode; int cce_secure; int ring_size; int usec_timeout; unsigned int fb_bpp; unsigned int front_offset, front_pitch; unsigned int back_offset, back_pitch; unsigned int depth_bpp; unsigned int depth_offset, depth_pitch; unsigned int span_offset; unsigned long fb_offset; unsigned long mmio_offset; unsigned long ring_offset; unsigned long ring_rptr_offset; unsigned long buffers_offset; unsigned long agp_textures_offset; } drm_r128_init_t; typedef struct drm_r128_cce_stop { int flush; int idle; } drm_r128_cce_stop_t; typedef struct drm_r128_clear { unsigned int flags; unsigned int clear_color; unsigned int clear_depth; unsigned int color_mask; unsigned int depth_mask; } drm_r128_clear_t; typedef struct drm_r128_vertex { int prim; int idx; /* Index of vertex buffer */ int count; /* Number of vertices in buffer */ int discard; /* Client finished with buffer? */ } drm_r128_vertex_t; typedef struct drm_r128_indices { int prim; int idx; int start; int end; int discard; /* Client finished with buffer? */ } drm_r128_indices_t; typedef struct drm_r128_blit { int idx; int pitch; int offset; int format; unsigned short x, y; unsigned short width, height; } drm_r128_blit_t; typedef struct drm_r128_depth { enum { R128_WRITE_SPAN = 0x01, R128_WRITE_PIXELS = 0x02, R128_READ_SPAN = 0x03, R128_READ_PIXELS = 0x04 } func; int n; int *x; int *y; unsigned int *buffer; unsigned char *mask; } drm_r128_depth_t; typedef struct drm_r128_stipple { unsigned int *mask; } drm_r128_stipple_t; typedef struct drm_r128_indirect { int idx; int start; int end; int discard; } drm_r128_indirect_t; typedef struct drm_r128_fullscreen { enum { R128_INIT_FULLSCREEN = 0x01, R128_CLEANUP_FULLSCREEN = 0x02 } func; } drm_r128_fullscreen_t; /* 2.3: An ioctl to get parameters that aren't available to the 3d * client any other way. */ #define R128_PARAM_IRQ_NR 1 typedef struct drm_r128_getparam { int param; void *value; } drm_r128_getparam_t; #endif /************************************************************************** * * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the * "Software"), to deal in the Software without restriction, including * without limitation the rights to use, copy, modify, merge, publish, * distribute, sub license, and/or sell copies of the Software, and to * permit persons to whom the Software is furnished to do so, subject to * the following conditions: * * The above copyright notice and this permission notice (including the * next paragraph) shall be included in all copies or substantial portions * of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. * **************************************************************************/ #ifndef __VMWGFX_DRM_H__ #define __VMWGFX_DRM_H__ #define DRM_VMW_MAX_SURFACE_FACES 6 #define DRM_VMW_MAX_MIP_LEVELS 24 #define DRM_VMW_EXT_NAME_LEN 128 #define DRM_VMW_GET_PARAM 0 #define DRM_VMW_ALLOC_DMABUF 1 #define DRM_VMW_UNREF_DMABUF 2 #define DRM_VMW_CURSOR_BYPASS 3 /* guarded by DRM_VMW_PARAM_NUM_STREAMS != 0*/ #define DRM_VMW_CONTROL_STREAM 4 #define DRM_VMW_CLAIM_STREAM 5 #define DRM_VMW_UNREF_STREAM 6 /* guarded by DRM_VMW_PARAM_3D == 1 */ #define DRM_VMW_CREATE_CONTEXT 7 #define DRM_VMW_UNREF_CONTEXT 8 #define DRM_VMW_CREATE_SURFACE 9 #define DRM_VMW_UNREF_SURFACE 10 #define DRM_VMW_REF_SURFACE 11 #define DRM_VMW_EXECBUF 12 #define DRM_VMW_FIFO_DEBUG 13 #define DRM_VMW_FENCE_WAIT 14 /* guarded by minor version >= 2 */ #define DRM_VMW_UPDATE_LAYOUT 15 /*************************************************************************/ /** * DRM_VMW_GET_PARAM - get device information. * * DRM_VMW_PARAM_FIFO_OFFSET: * Offset to use to map the first page of the FIFO read-only. * The fifo is mapped using the mmap() system call on the drm device. * * DRM_VMW_PARAM_OVERLAY_IOCTL: * Does the driver support the overlay ioctl. */ #define DRM_VMW_PARAM_NUM_STREAMS 0 #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 #define DRM_VMW_PARAM_3D 2 #define DRM_VMW_PARAM_FIFO_OFFSET 3 #define DRM_VMW_PARAM_HW_CAPS 4 #define DRM_VMW_PARAM_FIFO_CAPS 5 #define DRM_VMW_PARAM_MAX_FB_SIZE 6 /** * struct drm_vmw_getparam_arg * * @value: Returned value. //Out * @param: Parameter to query. //In. * * Argument to the DRM_VMW_GET_PARAM Ioctl. */ struct drm_vmw_getparam_arg { uint64_t value; uint32_t param; uint32_t pad64; }; /*************************************************************************/ /** * DRM_VMW_EXTENSION - Query device extensions. */ /** * struct drm_vmw_extension_rep * * @exists: The queried extension exists. * @driver_ioctl_offset: Ioctl number of the first ioctl in the extension. * @driver_sarea_offset: Offset to any space in the DRI SAREA * used by the extension. * @major: Major version number of the extension. * @minor: Minor version number of the extension. * @pl: Patch level version number of the extension. * * Output argument to the DRM_VMW_EXTENSION Ioctl. */ struct drm_vmw_extension_rep { int32_t exists; uint32_t driver_ioctl_offset; uint32_t driver_sarea_offset; uint32_t major; uint32_t minor; uint32_t pl; uint32_t pad64; }; /** * union drm_vmw_extension_arg * * @extension - Ascii name of the extension to be queried. //In * @rep - Reply as defined above. //Out * * Argument to the DRM_VMW_EXTENSION Ioctl. */ union drm_vmw_extension_arg { char extension[DRM_VMW_EXT_NAME_LEN]; struct drm_vmw_extension_rep rep; }; /*************************************************************************/ /** * DRM_VMW_CREATE_CONTEXT - Create a host context. * * Allocates a device unique context id, and queues a create context command * for the host. Does not wait for host completion. */ /** * struct drm_vmw_context_arg * * @cid: Device unique context ID. * * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. */ struct drm_vmw_context_arg { int32_t cid; uint32_t pad64; }; /*************************************************************************/ /** * DRM_VMW_UNREF_CONTEXT - Create a host context. * * Frees a global context id, and queues a destroy host command for the host. * Does not wait for host completion. The context ID can be used directly * in the command stream and shows up as the same context ID on the host. */ /*************************************************************************/ /** * DRM_VMW_CREATE_SURFACE - Create a host suface. * * Allocates a device unique surface id, and queues a create surface command * for the host. Does not wait for host completion. The surface ID can be * used directly in the command stream and shows up as the same surface * ID on the host. */ /** * struct drm_wmv_surface_create_req * * @flags: Surface flags as understood by the host. * @format: Surface format as understood by the host. * @mip_levels: Number of mip levels for each face. * An unused face should have 0 encoded. * @size_addr: Address of a user-space array of sruct drm_vmw_size * cast to an uint64_t for 32-64 bit compatibility. * The size of the array should equal the total number of mipmap levels. * @shareable: Boolean whether other clients (as identified by file descriptors) * may reference this surface. * @scanout: Boolean whether the surface is intended to be used as a * scanout. * * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. * Output data from the DRM_VMW_REF_SURFACE Ioctl. */ struct drm_vmw_surface_create_req { uint32_t flags; uint32_t format; uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; uint64_t size_addr; int32_t shareable; int32_t scanout; }; /** * struct drm_wmv_surface_arg * * @sid: Surface id of created surface or surface to destroy or reference. * * Output data from the DRM_VMW_CREATE_SURFACE Ioctl. * Input argument to the DRM_VMW_UNREF_SURFACE Ioctl. * Input argument to the DRM_VMW_REF_SURFACE Ioctl. */ struct drm_vmw_surface_arg { int32_t sid; uint32_t pad64; }; /** * struct drm_vmw_size ioctl. * * @width - mip level width * @height - mip level height * @depth - mip level depth * * Description of a mip level. * Input data to the DRM_WMW_CREATE_SURFACE Ioctl. */ struct drm_vmw_size { uint32_t width; uint32_t height; uint32_t depth; uint32_t pad64; }; /** * union drm_vmw_surface_create_arg * * @rep: Output data as described above. * @req: Input data as described above. * * Argument to the DRM_VMW_CREATE_SURFACE Ioctl. */ union drm_vmw_surface_create_arg { struct drm_vmw_surface_arg rep; struct drm_vmw_surface_create_req req; }; /*************************************************************************/ /** * DRM_VMW_REF_SURFACE - Reference a host surface. * * Puts a reference on a host surface with a give sid, as previously * returned by the DRM_VMW_CREATE_SURFACE ioctl. * A reference will make sure the surface isn't destroyed while we hold * it and will allow the calling client to use the surface ID in the command * stream. * * On successful return, the Ioctl returns the surface information given * in the DRM_VMW_CREATE_SURFACE ioctl. */ /** * union drm_vmw_surface_reference_arg * * @rep: Output data as described above. * @req: Input data as described above. * * Argument to the DRM_VMW_REF_SURFACE Ioctl. */ union drm_vmw_surface_reference_arg { struct drm_vmw_surface_create_req rep; struct drm_vmw_surface_arg req; }; /*************************************************************************/ /** * DRM_VMW_UNREF_SURFACE - Unreference a host surface. * * Clear a reference previously put on a host surface. * When all references are gone, including the one implicitly placed * on creation, * a destroy surface command will be queued for the host. * Does not wait for completion. */ /*************************************************************************/ /** * DRM_VMW_EXECBUF * * Submit a command buffer for execution on the host, and return a * fence sequence that when signaled, indicates that the command buffer has * executed. */ /** * struct drm_vmw_execbuf_arg * * @commands: User-space address of a command buffer cast to an uint64_t. * @command-size: Size in bytes of the command buffer. * @throttle-us: Sleep until software is less than @throttle_us * microseconds ahead of hardware. The driver may round this value * to the nearest kernel tick. * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an * uint64_t. * @version: Allows expanding the execbuf ioctl parameters without breaking * backwards compatibility, since user-space will always tell the kernel * which version it uses. * @flags: Execbuf flags. None currently. * * Argument to the DRM_VMW_EXECBUF Ioctl. */ #define DRM_VMW_EXECBUF_VERSION 0 struct drm_vmw_execbuf_arg { uint64_t commands; uint32_t command_size; uint32_t throttle_us; uint64_t fence_rep; uint32_t version; uint32_t flags; }; /** * struct drm_vmw_fence_rep * * @fence_seq: Fence sequence associated with a command submission. * @error: This member should've been set to -EFAULT on submission. * The following actions should be take on completion: * error == -EFAULT: Fence communication failed. The host is synchronized. * Use the last fence id read from the FIFO fence register. * error != 0 && error != -EFAULT: * Fence submission failed. The host is synchronized. Use the fence_seq member. * error == 0: All is OK, The host may not be synchronized. * Use the fence_seq member. * * Input / Output data to the DRM_VMW_EXECBUF Ioctl. */ struct drm_vmw_fence_rep { uint64_t fence_seq; int32_t error; uint32_t pad64; }; /*************************************************************************/ /** * DRM_VMW_ALLOC_DMABUF * * Allocate a DMA buffer that is visible also to the host. * NOTE: The buffer is * identified by a handle and an offset, which are private to the guest, but * useable in the command stream. The guest kernel may translate these * and patch up the command stream accordingly. In the future, the offset may * be zero at all times, or it may disappear from the interface before it is * fixed. * * The DMA buffer may stay user-space mapped in the guest at all times, * and is thus suitable for sub-allocation. * * DMA buffers are mapped using the mmap() syscall on the drm device. */ /** * struct drm_vmw_alloc_dmabuf_req * * @size: Required minimum size of the buffer. * * Input data to the DRM_VMW_ALLOC_DMABUF Ioctl. */ struct drm_vmw_alloc_dmabuf_req { uint32_t size; uint32_t pad64; }; /** * struct drm_vmw_dmabuf_rep * * @map_handle: Offset to use in the mmap() call used to map the buffer. * @handle: Handle unique to this buffer. Used for unreferencing. * @cur_gmr_id: GMR id to use in the command stream when this buffer is * referenced. See not above. * @cur_gmr_offset: Offset to use in the command stream when this buffer is * referenced. See note above. * * Output data from the DRM_VMW_ALLOC_DMABUF Ioctl. */ struct drm_vmw_dmabuf_rep { uint64_t map_handle; uint32_t handle; uint32_t cur_gmr_id; uint32_t cur_gmr_offset; uint32_t pad64; }; /** * union drm_vmw_dmabuf_arg * * @req: Input data as described above. * @rep: Output data as described above. * * Argument to the DRM_VMW_ALLOC_DMABUF Ioctl. */ union drm_vmw_alloc_dmabuf_arg { struct drm_vmw_alloc_dmabuf_req req; struct drm_vmw_dmabuf_rep rep; }; /***************************************************************s¹t¹u¹v¹w¹**********/ /** * DRM_VMW_UNREF_DMABUF - Free a DMA buffer. * */ /** * struct drm_vmw_unref_dmabuf_arg * * @handle: Handle indicating what buffer to free. Obtained from the * DRM_VMW_ALLOC_DMABUF Ioctl. * * Argument to the DRM_VMW_UNREF_DMABUF Ioctl. */ struct drm_vmw_unref_dmabuf_arg { uint32_t handle; uint32_t pad64; }; /*************************************************************************/ /** * DRM_VMW_FIFO_DEBUG - Get last FIFO submission. * * This IOCTL copies the last FIFO submission directly out of the FIFO buffer. */ /** * struct drm_vmw_fifo_debug_arg * * @debug_buffer: User space address of a debug_buffer cast to an uint64_t //In * @debug_buffer_size: Size in bytes of debug buffer //In * @used_size: Number of bytes copied to the buffer // Out * @did_not_fit: Boolean indicating that the fifo contents did not fit. //Out * * Argument to the DRM_VMW_FIFO_DEBUG Ioctl. */ struct drm_vmw_fifo_debug_arg { uint64_t debug_buffer; uint32_t debug_buffer_size; uint32_t used_size; int32_t did_not_fit; uint32_t pad64; }; struct drm_vmw_fence_wait_arg { uint64_t sequence; uint64_t kernel_cookie; int32_t cookie_valid; int32_t pad64; }; /*************************************************************************/ /** * DRM_VMW_CONTROL_STREAM - Control overlays, aka streams. * * This IOCTL controls the overlay units of the svga device. * The SVGA overlay units does not work like regular hardware units in * that they do not automaticaly read back the contents of the given dma * buffer. But instead only read back for each call to this ioctl, and * at any point between this call being made and a following call that * either changes the buffer or disables the stream. */ /** * struct drm_vmw_rect * * Defines a rectangle. Used in the overlay ioctl to define * source and destination rectangle. */ struct drm_vmw_rect { int32_t x; int32_t y; uint32_t w; uint32_t h; }; /** * struct drm_vmw_control_stream_arg * * @stream_id: Stearm to control * @enabled: If false all following arguments are ignored. * @handle: Handle to buffer for getting data from. * @format: Format of the overlay as understood by the host. * @width: Width of the overlay. * @height: Height of the overlay. * @size: Size of the overlay in bytes. * @pitch: Array of pitches, the two last are only used for YUV12 formats. * @offset: Offset from start of dma buffer to overlay. * @src: Source rect, must be within the defined area above. * @dst: Destination rect, x and y may be negative. * * Argument to the DRM_VMW_CONTROL_STREAM Ioctl. */ struct drm_vmw_control_stream_arg { uint32_t stream_id; uint32_t enabled; uint32_t flags; uint32_t color_key; uint32_t handle; uint32_t offset; int32_t format; uint32_t size; uint32_t width; uint32_t height; uint32_t pitch[3]; uint32_t pad64; struct drm_vmw_rect src; struct drm_vmw_rect dst; }; /*************************************************************************/ /** * DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass. * */ #define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0) #define DRM_VMW_CURSOR_BYPASS_FLAGS (1) /** * struct drm_vmw_cursor_bypass_arg * * @flags: Flags. * @crtc_id: Crtc id, only used if DMR_CURSOR_BYPASS_ALL isn't passed. * @xpos: X position of cursor. * @ypos: Y position of cursor. * @xhot: X hotspot. * @yhot: Y hotspot. * * Argument to the DRM_VMW_CURSOR_BYPASS Ioctl. */ struct drm_vmw_cursor_bypass_arg { uint32_t flags; uint32_t crtc_id; int32_t xpos; int32_t ypos; int32_t xhot; int32_t yhot; }; /*************************************************************************/ /** * DRM_VMW_CLAIM_STREAM - Claim a single stream. */ /** * struct drm_vmw_context_arg * * @stream_id: Device unique context ID. * * Output argument to the DRM_VMW_CREATE_CONTEXT Ioctl. * Input argument to the DRM_VMW_UNREF_CONTEXT Ioctl. */ struct drm_vmw_stream_arg { uint32_t stream_id; uint32_t pad64; }; /*************************************************************************/ /** * DRM_VMW_UNREF_STREAM - Unclaim a stream. * * Return a single stream that was claimed by this process. Also makes * sure that the stream has been stopped. */ /*************************************************************************/ /** * DRM_VMW_UPDATE_LAYOUT - Update layout * * Updates the prefered modes and connection status for connectors. The * command conisits of one drm_vmw_update_layout_arg pointing out a array * of num_outputs drm_vmw_rect's. */ /** * struct drm_vmw_update_layout_arg * * @num_outputs: number of active * @rects: pointer to array of drm_vmw_rect * * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. */ struct drm_vmw_update_layout_arg { uint32_t num_outputs; uint32_t pad64; uint64_t rects; }; #endif /* sis_drv.h -- Private header for sis driver -*- linux-c -*- */ /* * Copyright 2005 Eric Anholt * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * */ #ifndef __SIS_DRM_H__ #define __SIS_DRM_H__ /* SiS specific ioctls */ #define NOT_USED_0_3 #define DRM_SIS_FB_ALLOC 0x04 #define DRM_SIS_FB_FREE 0x05 #define NOT_USED_6_12 #define DRM_SIS_AGP_INIT 0x13 #define DRM_SIS_AGP_ALLOC 0x14 #define DRM_SIS_AGP_FREE 0x15 #define DRM_SIS_FB_INIT 0x16 #define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t) #define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t) #define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t) #define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t) #define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t) #define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t) /* #define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t) #define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49) #define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50) */ typedef struct { int context; unsigned int offset; unsigned int size; unsigned long free; } drm_sis_mem_t; typedef struct { unsigned int offset, size; } drm_sis_agp_t; typedef struct { unsigned int offset, size; } drm_sis_fb_t; #endif /* __SIS_DRM_H__ */ #ifndef _I830_DRM_H_ #define _I830_DRM_H_ /* WARNING: These defines must be the same as what the Xserver uses. * if you change them, you must change the defines in the Xserver. * * KW: Actually, you can't ever change them because doing so would * break backwards compatibility. */ #ifndef _I830_DEFINES_ #define _I830_DEFINES_ #define I830_DMA_BUF_ORDER 12 #define I830_DMA_BUF_SZ (1<