ructions. This option can only be used when generating 64-bit code and requires hardware floating-point support to be enabled. `-mips3d' `-mno-mips3d' Use (do not use) the MIPS-3D ASE. *Note MIPS-3D Built-in Functions::. The option `-mips3d' implies `-mpaired-single'. `-mmt' `-mno-mt' Use (do not use) MT Multithreading instructions. `-mlong64' Force `long' types to be 64 bits wide. See `-mlong32' for an explanation of the default and the way that the pointer size is determined. `-mlong32' Force `long', `int', and pointer types to be 32 bits wide. The default size of `int's, `long's and pointers depends on the ABI. All the supported ABIs use 32-bit `int's. The n64 ABI uses 64-bit `long's, as does the 64-bit EABI; the others use 32-bit `long's. Pointers are the same size as `long's, or the same size as integer registers, whichever is smaller. `-msym32' `-mno-sym32' Assume (do not assume) that all symbols have 32-bit values, regardless of the selected ABI. This option is useful in combination with `-mabi=64' and `-mno-abicalls' because it allows GCC to generate shorter and faster references to symbolic addresses. `-G NUM' Put definitions of externally-visible data in a small data section if that data is no bigger than NUM bytes. GCC can then access the data more efficiently; see `-mgpopt' for details. The default `-G' option depends on the configuration. `-mlocal-sdata' `-mno-local-sdata' Extend (do not extend) the `-G' behavior to local data too, such as to static variables in C. `-mlocal-sdata' is the default for all configurations. If the linker complains that an application is using too much small data, you might want to try rebuilding the less performance-critical parts with `-mno-local-sdata'. You might also want to build large libraries with `-mno-local-sdata', so that the libraries leave more room for the main program. `-mextern-sdata' `-mno-extern-sdata' Assume (do not assume) that externally-defined data will be in a small data section if that data is within the `-G' limit. `-mextern-sdata' is the default for all configurations. If you compile a module MOD with `-mextern-sdata' `-G NUM' `-mgpopt', and MOD references a variable VAR that is no bigger than NUM bytes, you must make sure that VAR is placed in a small data section. If VAR is defined by another module, you must either compile that module with a high-enough `-G' setting or attach a `section' attribute to VAR's definition. If VAR is common, you must link the application with a high-enough `-G' setting. The easiest way of satisfying these restrictions is to compile and link every module with the same `-G' option. However, you may wish to build a library that supports several different small data limits. You can do this by compiling the library with the highest supported `-G' setting and additionally using `-mno-extern-sdata' to stop the library from making assumptions about externally-defined data. `-mgpopt' `-mno-gpopt' Use (do not use) GP-relative accesses for symbols that are known to be in a small data section; see `-G', `-mlocal-sdata' and `-mextern-sdata'. `-mgpopt' is the default for all configurations. `-mno-gpopt' is useful for cases where the `$gp' register might not hold the value of `_gp'. For example, if the code is part of a library that might be used in a boot monitor, programs that call boot monitor routines will pass an unknown value in `$gp'. (In such situations, the boot monitor itself would usually be compiled with `-G0'.) `-mno-gpopt' implies `-mno-local-sdata' and `-mno-extern-sdata'. `-membedded-data' `-mno-embedded-data' Allocate variables to the read-only data section first if possible, then next in the small data section if possible, otherwise in data. This gives slightly slower code than the default, but reduces the amount of RAM required when executing, and thus may be preferred for some embedded systems. `-muninit-const-in-rodata' `-mno-uninit-const-in-rodata' Put uninitialized `const' variables in the read-only data section. This option is only meaningful in conjunction with `-membedded-data'. `-mcode-readable=SETTING' Specify whether GCC may generate code that reads from executable sections. There are three possible settings: `-mcode-readable=yes' Instructions may freely access executable sections. This is the default setting. `-mcode-readable=pcrel' MIPS16 PC-relative load instructions can access executable sections, but other instructions must not do so. This option is useful on 4KSc and 4KSd processors when the code TLBs have the Read Inhibit bit set. It is also useful on processors that can be configured to have a dual instruction/data SRAM interface and that, like the M4K, automatically redirect PC-relative loads to the instruction RAM. `-mcode-readable=no' Instructions must not access executable sections. This option can be useful on targets that are configured to have a dual instruction/data SRAM interface but that (unlike the M4K) do not automatically redirect PC-relative loads to the instruction RAM. `-msplit-addresses' `-mno-split-addresses' Enable (disable) use of the `%hi()' and `%lo()' assembler relocation operators. This option has been superseded by `-mexplicit-relocs' but is retained for backwards compatibility. `-mexplicit-relocs' `-mno-explicit-relocs' Use (do not use) assembler relocation operators when dealing with symbolic addresses. The alternative, selected by `-mno-explicit-relocs', is to use assembler macros instead. `-mexplicit-relocs' is the default if GCC was configured to use an assembler that supports relocation operators. `-mcheck-zero-division' `-mno-check-zero-division' Trap (do not trap) on integer division by zero. The default is `-mcheck-zero-division'. `-mdivide-traps' `-mdivide-breaks' MIPS systems check for division by zero by generating either a conditional trap or a break instruction. Using traps results in smaller code, but is only supported on MIPS II and later. Also, some versions of the Linux kernel have a bug that prevents trap from generating the proper signal (`SIGFPE'). Use `-mdivide-traps' to allow conditional traps on architectures that support them and `-mdivide-breaks' to force the use of breaks. The default is usually `-mdivide-traps', but this can be overridden at configure time using `--with-divide=breaks'. Divide-by-zero checks can be completely disabled using `-mno-check-zero-division'. `-mmemcpy' `-mno-memcpy' Force (do not force) the use of `memcpy()' for non-trivial block moves. The default is `-mno-memcpy', which allows GCC to inline most constant-sized copies. `-mlong-calls' `-mno-long-calls' Disable (do not disable) use of the `jal' instruction. Calling functions using `jal' is more efficient but requires the caller and callee to be in the same 256 megabyte segment. This option has no effect on abicalls code. The default is `-mno-long-calls'. `-mmad' `-mno-mad' Enable (disable) use of the `mad', `madu' and `mul' instructions, as provided by the R4650 ISA. `-mfused-madd' `-mno-fused-madd' Enable (disable) use of the floating point multiply-accumulate instructions, when they are available. The default is `-mfused-madd'. When multiply-accumulate instructions are used, the intermediate product is calculated to infinite precision and is not subject to the FCSR Flush to Zero bit. This may be undesirable in some circumstances. `-nocpp' Tell the MIPS assembler to not run its preprocessor over user assembler files (with a `.s' suffix) when assembling them. `-mfix-r4000' `-mno-fix-r4000' Work around certain R4000 CPU errata: - A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division. - A double-word or a variable shift may give an incorrect result if executed while an integer multiplication is in progress. - An integer division may give an incorrect result if started in a delay slot of a taken branch or a jump. `-mfix-r4400' `-mno-fix-r4400' Work around certain R4400 CPU errata: - A double-word or a variable shift may give an incorrect result if executed immediately after starting an integer division. `-mfix-vr4120' `-mno-fix-vr4120' Work around certain VR4120 errata: - `dmultu' does not always produce the correct result. - `div' and `ddiv' do not always produce the correct result if one of the operands is negative. The workarounds for the division errata rely on special functions in `libgcc.a'. At present, these functions are only provided by the `mips64vr*-elf' configurations. Other VR4120 errata require a nop to be inserted between certain pairs of instructions. These errata are handled by the assembler, not by GCC itself. `-mfix-vr4130' Work around the VR4130 `mflo'/`mfhi' errata. The workarounds are implemented by the assembler rather than by GCC, although GCC will avoid using `mflo' and `mfhi' if the VR4130 `macc', `macchi', `dmacc' and `dmacchi' instructions are available instead. `-mfix-sb1' `-mno-fix-sb1' Work around certain SB-1 CPU core errata. (This flag currently works around the SB-1 revision 2 "F1" and "F2" floating point errata.) `-mflush-func=FUNC' `-mno-flush-func' Specifies the function to call to flush the I and D caches, or to not call any such function. If called, the function must take the same arguments as the common `_flush_func()', that is, the address of the memory range for which the cache is being flushed, the size of the memory range, and the number 3 (to flush both caches). The default depends on the target GCC was configured for, but commonly is either `_flush_func' or `__cpu_flush'. `mbranch-cost=NUM' Set the cost of branches to roughly NUM "simple" instructions. This cost is only a heuristic and is not guaranteed to produce consistent results across releases. A zero cost redundantly selects the default, which is based on the `-mtune' setting. `-mbranch-likely' `-mno-branch-likely' Enable or disable use of Branch Likely instructions, regardless of the default for the selected architecture. By default, Branch Likely instructions may be generated if they are supported by the selected architecture. An exception is for the MIPS32 and MIPS64 architectures and processors which implement those architectures; for those, Branch Likely instructions will not be generated by default because the MIPS32 and MIPS64 architectures specifically deprecate their use. `-mfp-exceptions' `-mno-fp-exceptions' Specifies whether FP exceptions are enabled. This affects how we schedule FP instructions for some processors. The default is that FP exceptions are enabled. For instance, on the SB-1, if FP exceptions are disabled, and we are emitting 64-bit code, then we can use both FP pipes. Otherwise, we can only use one FP pipe. `-mvr4130-align' `-mno-vr4130-align' The VR4130 pipeline is two-way superscalar, but can only issue two instructions together if the first one is 8-byte aligned. When this option is enabled, GCC will align pairs of instructions that it thinks should execute in parallel. This option only has an effect when optimizing for the VR4130. It normally makes code faster, but at the expense of making it bigger. It is enabled by default at optimization level `-O3'.  File: gcc.info, Node: MMIX Options, Next: MN10300 Options, Prev: MIPS Options, Up: Submodel Options 3.17.22 MMIX Options -------------------- These options are defined for the MMIX: `-mlibfuncs' `-mno-libfuncs' Specify that intrinsic library functions are being compiled, passing all values in registers, no matter the size. `-mepsilon' `-mno-epsilon' Generate floating-point comparison instructions that compare with respect to the `rE' epsilon register. `-mabi=mmixware' `-mabi=gnu' Generate code that passes function parameters and return values that (in the called function) are seen as registers `$0' and up, as opposed to the GNU ABI which uses global registers `$231' and up. `-mzero-extend' `-mno-zero-extend' When reading data from memory in sizes shorter than 64 bits, use (do not use) zero-extending load instructions by default, rather than sign-extending ones. `-mknuthdiv' `-mno-knuthdiv' Make the result of a division yielding a remainder have the same sign as the divisor. With the default, `-mno-knuthdiv', the sign of the remainder follows the sign of the dividend. Both methods are arithmetically valid, the latter being almost exclusively used. `-mtoplevel-symbols' `-mno-toplevel-symbols' Prepend (do not prepend) a `:' to all global symbols, so the assembly code can be used with the `PREFIX' assembly directive. `-melf' Generate an executable in the ELF format, rather than the default `mmo' format used by the `mmix' simulator. `-mbranch-predict' `-mno-branch-predict' Use (do not use) the probable-branch instructions, when static branch prediction indicates a probable branch. `-mbase-addresses' `-mno-base-addresses' Generate (do not generate) code that uses _base addresses_. Using a base address automatically generates a request (handled by the assembler and the linker) for a constant to be set up in a global register. The register is used for one or more base address requests within the range 0 to 255 from the value held in the register. The generally leads to short and fast code, but the number of different data items that can be addressed is limited. This means that a program that uses lots of static data may require `-mno-base-addresses'. `-msingle-exit' `-mno-single-exit' Force (do not force) generated code to have a single exit point in each function.  File: gcc.info, Node: MN10300 Options, Next: MT Options, Prev: MMIX Options, Up: Submodel Options 3.17.23 MN10300 Options ----------------------- These `-m' options are defined for Matsushita MN10300 architectures: `-mmult-bug' Generate code to avoid bugs in the multiply instructions for the MN10300 processors. This is the default. `-mno-mult-bug' Do not generate code to avoid bugs in the multiply instructions for the MN10300 processors. `-mam33' Generate code which uses features specific to the AM33 processor. `-mno-am33' Do not generate code which uses features specific to the AM33 processor. This is the default. `-mreturn-pointer-on-d0' When generating a function which returns a pointer, return the pointer in both `a0' and `d0'. Otherwise, the pointer is returned only in a0, and attempts to call such functions without a prototype would result in errors. Note that this option is on by default; use `-mno-return-pointer-on-d0' to disable it. `-mno-crt0' Do not link in the C run-time initialization object file. `-mrelax' Indicate to the linker that it should perform a relaxation optimization pass to shorten branches, calls and absolute memory addresses. This option only has an effect when used on the command line for the final link step. This option makes symbolic debugging impossible.  File: gcc.info, Node: MT Options, Next: PDP-11 Options, Prev: MN10300 Options, Up: Submodel Options 3.17.24 MT Options ------------------ These `-m' options are defined for Morpho MT architectures: `-march=CPU-TYPE' Generate code that will run on CPU-TYPE, which is the name of a system representing a certain processor type. Possible values for CPU-TYPE are `ms1-64-001', `ms1-16-002', `ms1-16-003' and `ms2'. When this option is not used, the default is `-march=ms1-16-002'. `-mbacc' Use byte loads and stores when generating code. `-mno-bacc' Do not use byte loads and stores when generating code. `-msim' Use simulator runtime `-mno-crt0' Do not link in the C run-time initialization object file `crti.o'. Other run-time initialization and termination files such as `startup.o' and `exit.o' are still included on the linker command line.  File: gcc.info, Node: PDP-11 Options, Next: PowerPC Options, Prev: MT Options, Up: Submodel Options 3.17.25 PDP-11 Options ---------------------- These options are defined for the PDP-11: `-mfpu' Use hardware FPP floating point. This is the default. (FIS floating point on the PDP-11/40 is not supported.) `-msoft-float' Do not use hardware floating point. `-mac0' Return floating-point results in ac0 (fr0 in Unix assembler syntax). `-mno-ac0' Return floating-point results in memory. This is the default. `-m40' Generate code for a PDP-11/40. `-m45' Generate code for a PDP-11/45. This is the default. `-m10' Generate code for a PDP-11/10. `-mbcopy-builtin' Use inline `movmemhi' patterns for copying memory. This is the default. `-mbcopy' Do not use inline `movmemhi' patterns for copying memory. `-mint16' `-mno-int32' Use 16-bit `int'. This is the default. `-mint32' `-mno-int16' Use 32-bit `int'. `-mfloat64' `-mno-float32' Use 64-bit `float'. This is the default. `-mfloat32' `-mno-float64' Use 32-bit `float'. `-mabshi' Use `abshi2' pattern. This is the default. `-mno-abshi' Do not use `abshi2' pattern. `-mbranch-expensive' Pretend that branches are expensive. This is for experimenting with code generation only. `-mbranch-cheap' Do not pretend that branches are expensive. This is the default. `-msplit' Generate code for a system with split I&D. `-mno-split' Generate code for a system without split I&D. This is the default. `-munix-asm' Use Unix assembler syntax. This is the default when configured for `pdp11-*-bsd'. `-mdec-asm' Use DEC assembler syntax. This is the default when configured for any PDP-11 target other than `pdp11-*-bsd'.  File: gcc.info, Node: PowerPC Options, Next: RS/6000 and PowerPC Options, Prev: PDP-11 Options, Up: Submodel Options 3.17.26 PowerPC Options ----------------------- These are listed under *Note RS/6000 and PowerPC Options::.  File: gcc.info, Node: RS/6000 and PowerPC Options, Next: S/390 and zSeries Options, Prev: PowerPC Options, Up: Submodel Options 3.17.27 IBM RS/6000 and PowerPC Options --------------------------------------- These `-m' options are defined for the IBM RS/6000 and PowerPC: `-mpower' `-mno-power' `-mpower2' `-mno-power2' `-mpowerpc' `-mno-powerpc' `-mpowerpc-gpopt' `-mno-powerpc-gpopt' `-mpowerpc-gfxopt' `-mno-powerpc-gfxopt' `-mpowerpc64' `-mno-powerpc64' `-mmfcrf' `-mno-mfcrf' `-mpopcntb' `-mno-popcntb' `-mfprnd' `-mno-fprnd' `-mcmpb' `-mno-cmpb' `-mmfpgpr' `-mno-mfpgpr' `-mhard-dfp' `-mno-hard-dfp' GCC supports two related instruction set architectures for the RS/6000 and PowerPC. The "POWER" instruction set are those instructions supported by the `rios' chip set used in the original RS/6000 systems and the "PowerPC" instruction set is the architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and the IBM 4xx, 6xx, and follow-on microprocessors. Neither architecture is a subset of the other. However there is a large common subset of instructions supported by both. An MQ register is included in processors supporting the POWER architecture. You use these options to specify which instructions are available on the processor you are using. The default value of these options is determined when configuring GCC. Specifying the `-mcpu=CPU_TYPE' overrides the specification of these options. We recommend you use the `-mcpu=CPU_TYPE' option rather than the options listed above. The `-mpower' option allows GCC to generate instructions that are found only in the POWER architecture and to use the MQ register. Specifying `-mpower2' implies `-power' and also allows GCC to generate instructions that are present in the POWER2 architecture but not the original POWER architecture. The `-mpowerpc' option allows GCC to generate instructions that are found only in the 32-bit subset of the PowerPC architecture. Specifying `-mpowerpc-gpopt' implies `-mpowerpc' and also allows GCC to use the optional PowerPC architecture instructions in the General Purpose group, including floating-point square root. Specifying `-mpowerpc-gfxopt' implies `-mpowerpc' and also allows GCC to use the optional PowerPC architecture instructions in the Graphics group, including floating-point select. The `-mmfcrf' option allows GCC to generate the move from condition register field instruction implemented on the POWER4 processor and other processors that support the PowerPC V2.01 architecture. The `-mpopcntb' option allows GCC to generate the popcount and double precision FP reciprocal estimate instruction implemented on the POWER5 processor and other processors that support the PowerPC V2.02 architecture. The `-mfprnd' option allows GCC to generate the FP round to integer instructions implemented on the POWER5+ processor and other processors that support the PowerPC V2.03 architecture. The `-mcmpb' option allows GCC to generate the compare bytes instruction implemented on the POWER6 processor and other processors that support the PowerPC V2.05 architecture. The `-mmfpgpr' option allows GCC to generate the FP move to/from general purpose register instructions implemented on the POWER6X processor and other processors that support the extended PowerPC V2.05 architecture. The `-mhard-dfp' option allows GCC to generate the decimal floating point instructions implemented on some POWER processors. The `-mpowerpc64' option allows GCC to generate the additional 64-bit instructions that are found in the full PowerPC64 architecture and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to `-mno-powerpc64'. If you specify both `-mno-power' and `-mno-powerpc', GCC will use only the instructions in the common subset of both architectures plus some special AIX common-mode calls, and will not use the MQ register. Specifying both `-mpower' and `-mpowerpc' permits GCC to use any instruction from either architecture and to allow use of the MQ register; specify this for the Motorola MPC601. `-mnew-mnemonics' `-mold-mnemonics' Select which mnemonics to use in the generated assembler code. With `-mnew-mnemonics', GCC uses the assembler mnemonics defined for the PowerPC architecture. With `-mold-mnemonics' it uses the assembler mnemonics defined for the POWER architecture. Instructions defined in only one architecture have only one mnemonic; GCC uses that mnemonic irrespective of which of these options is specified. GCC defaults to the mnemonics appropriate for the architecture in use. Specifying `-mcpu=CPU_TYPE' sometimes overrides the value of these option. Unless you are building a cross-compiler, you should normally not specify either `-mnew-mnemonics' or `-mold-mnemonics', but should instead accept the default. `-mcpu=CPU_TYPE' Set architecture type, register usage, choice of mnemonics, and instruction scheduling parameters for machine type CPU_TYPE. Supported values for CPU_TYPE are `401', `403', `405', `405fp', `440', `440fp', `505', `601', `602', `603', `603e', `604', `604e', `620', `630', `740', `7400', `7450', `750', `801', `821', `823', `860', `970', `8540', `ec603e', `G3', `G4', `G5', `power', `power2', `power3', `power4', `power5', `power5+', `power6', `power6x', `common', `powerpc', `powerpc64', `rios', `rios1', `rios2', `rsc', and `rs64'. `-mcpu=common' selects a completely generic processor. Code generated under this option will run on any POWER or PowerPC processor. GCC will use only the instructions in the common subset of both architectures, and will not use the MQ register. GCC assumes a generic processor model for scheduling purposes. `-mcpu=power', `-mcpu=power2', `-mcpu=powerpc', and `-mcpu=powerpc64' specify generic POWER, POWER2, pure 32-bit PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine types, with an appropriate, generic processor model assumed for scheduling purposes. The other options specify a specific processor. Code generated under those options will run best on that processor, and may not run at all on others. The `-mcpu' options automatically enable or disable the following options: -maltivec -mfprnd -mhard-float -mmfcrf -mmultiple -mnew-mnemonics -mpopcntb -mpower -mpower2 -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -mstring -mmulhw -mdlmzb -mmfpgpr The particular options set for any particular CPU will vary between compiler versions, depending on what setting seems to produce optimal code for that CPU; it doesn't necessarily reflect the actual hardware's capabilities. If you wish to set an individual option to a particular value, you may specify it after the `-mcpu' option, like `-mcpu=970 -mno-altivec'. On AIX, the `-maltivec' and `-mpowerpc64' options are not enabled or disabled by the `-mcpu' option at present because AIX does not have full support for these options. You may still enable or disable them individually if you're sure it'll work in your environment. `-mtune=CPU_TYPE' Set the instruction scheduling parameters for machine type CPU_TYPE, but do not set the architecture type, register usage, or choice of mnemonics, as `-mcpu=CPU_TYPE' would. The same values for CPU_TYPE are used for `-mtune' as for `-mcpu'. If both are specified, the code generated will use the architecture, registers, and mnemonics set by `-mcpu', but the scheduling parameters set by `-mtune'. `-mswdiv' `-mno-swdiv' Generate code to compute division as reciprocal estimate and iterative refinement, creating opportunities for increased throughput. This feature requires: optional PowerPC Graphics instruction set for single precision and FRE instruction for double precision, assuming divides cannot generate user-visible traps, and the domain values not include Infinities, denormals or zero denominator. `-maltivec' `-mno-altivec' Generate code that uses (does not use) AltiVec instructions, and also enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set `-mabi=altivec' to adjust the current ABI with AltiVec ABI enhancements. `-mvrsave' `-mno-vrsave' Generate VRSAVE instructions when generating AltiVec code. `-msecure-plt' Generate code that allows ld and ld.so to build executables and shared libraries with non-exec .plt and .got sections. This is a PowerPC 32-bit SYSV ABI option. `-mbss-plt' Generate code that uses a BSS .plt section that ld.so fills in, and requires .plt and .got sections that are both writable and executable. This is a PowerPC 32-bit SYSV ABI option. `-misel' `-mno-isel' This switch enables or disables the generation of ISEL instructions. `-misel=YES/NO' This switch has been deprecated. Use `-misel' and `-mno-isel' instead. `-mspe' `-mno-spe' This switch enables or disables the generation of SPE simd instructions. `-mpaired' `-mno-paired' This switch enables or disables the generation of PAIRED simd instructions. `-mspe=YES/NO' This option has been deprecated. Use `-mspe' and `-mno-spe' instead. `-mfloat-gprs=YES/SINGLE/DOUBLE/NO' `-mfloat-gprs' This switch enables or disables the generation of floating point operations on the general purpose registers for architectures that support it. The argument YES or SINGLE enables the use of single-precision floating point operations. The argument DOUBLE enables the use of single and double-precision floating point operations. The argument NO disables floating point operations on the general purpose registers. This option is currently only available on the MPC854x. `-m32' `-m64' Generate code for 32-bit or 64-bit environments of Darwin and SVR4 targets (including GNU/Linux). The 32-bit environment sets int, long and pointer to 32 bits and generates code that runs on any PowerPC variant. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits, and generates code for PowerPC64, as for `-mpowerpc64'. `-mfull-toc' `-mno-fp-in-toc' `-mno-sum-in-toc' `-mminimal-toc' Modify generation of the TOC (Table Of Contents), which is created for every executable file. The `-mfull-toc' option is selected by default. In that case, GCC will allocate at least one TOC entry for each unique non-automatic variable reference in your program. GCC will also place floating-point constants in the TOC. However, only 16,384 entries are available in the TOC. If you receive a linker error message that saying you have overflowed the available TOC space, you can reduce the amount of TOC space used with the `-mno-fp-in-toc' and `-mno-sum-in-toc' options. `-mno-fp-in-toc' prevents GCC from putting floating-point constants in the TOC and `-mno-sum-in-toc' forces GCC to generate code to calculate the sum of an address and a constant at run-time instead of putting that sum into the TOC. You may specify one or both of these options. Each causes GCC to produce very slightly slower and larger code at the expense of conserving TOC space. If you still run out of space in the TOC even when you specify both of these options, specify `-mminimal-toc' instead. This option causes GCC to make only one TOC entry for every file. When you specify this option, GCC will produce code that is slower and larger but which uses extremely little TOC space. You may wish to use this option only on files that contain less frequently executed code. `-maix64' `-maix32' Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit `long' type, and the infrastructure needed to support them. Specifying `-maix64' implies `-mpowerpc64' and `-mpowerpc', while `-maix32' disables the 64-bit ABI and implies `-mno-powerpc64'. GCC defaults to `-maix32'. `-mxl-compat' `-mno-xl-compat' Produce code that conforms more closely to IBM XL compiler semantics when using AIX-compatible ABI. Pass floating-point arguments to prototyped functions beyond the register save area (RSA) on the stack in addition to argument FPRs. Do not assume that most significant double in 128-bit long double value is properly rounded when comparing values and converting to double. Use XL symbol names for long double support routines. The AIX calling convention was extended but not initially documented to handle an obscure K&R C case of calling a function that takes the address of its arguments with fewer arguments than declared. IBM XL compilers access floating point arguments which do not fit in the RSA from the stack when a subroutine is compiled without optimization. Because always storing floating-point arguments on the stack is inefficient and rarely needed, this option is not enabled by default and only is necessary when calling subroutines compiled by IBM XL compilers without optimization. `-mpe' Support "IBM RS/6000 SP" "Parallel Environment" (PE). Link an application written to use message passing with special startup code to enable the application to run. The system must have PE installed in the standard location (`/usr/lpp/ppe.poe/'), or the `specs' file must be overridden with the `-specs=' option to specify the appropriate directory location. The Parallel Environment does not support threads, so the `-mpe' option and the `-pthread' option are incompatible. `-malign-natural' `-malign-power' On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option `-malign-natural' overrides the ABI-defined alignment of larger types, such as floating-point doubles, on their natural size-based boundary. The option `-malign-power' instructs GCC to follow the ABI-specified alignment rules. GCC defaults to the standard alignment defined in the ABI. On 64-bit Darwin, natural alignment is the default, and `-malign-power' is not supported. `-msoft-float' `-mhard-float' Generate code that does not use (uses) the floating-point register set. Software floating point emulation is provided if you use the `-msoft-float' option, and pass the option to GCC when linking. `-mmultiple' `-mno-multiple' Generate code that uses (does not use) the load multiple word instructions and the store multiple word instructions. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use `-mmultiple' on little endian PowerPC systems, since those instructions do not work when the processor is in little endian mode. The exceptions are PPC740 and PPC750 which permit the instructions usage in little endian mode. `-mstring' `-mno-string' Generate code that uses (does not use) the load string instructions and the store string word instructions to save multiple registers and do small block moves. These instructions are generated by default on POWER systems, and not generated on PowerPC systems. Do not use `-mstring' on little endian PowerPC systems, since those instructions do not work when the processor is in little endian mode. The exceptions are PPC740 and PPC750 which permit the instructions usage in little endian mode. `-mupdate' `-mno-update' Generate code that uses (does not use) the load or store instructions that update the base register to the address of the calculated memory location. These instructions are generated by default. If you use `-mno-update', there is a small window between the time that the stack pointer is updated and the address of the previous frame is stored, which means code that walks the stack frame across interrupts or signals may get corrupted data. `-mfused-madd' `-mno-fused-madd' Generate code that uses (does not use) the floating point multiply and accumulate instructions. These instructions are generated by default if hardware floating is used. `-mmulhw' `-mno-mulhw' Generate code that uses (does not use) the half-word multiply and multiply-accumulate instructions on the IBM 405 and 440 processors. These instructions are generated by default when targetting those processors. `-mdlmzb' `-mno-dlmzb' Generate code that uses (does not use) the string-search `dlmzb' instruction on the IBM 405 and 440 processors. This instruction is generated by default when targetting those processors. `-mno-bit-align' `-mbit-align' On System V.4 and embedded PowerPC systems do not (do) force structures and unions that contain bit-fields to be aligned to the base type of the bit-field. For example, by default a structure containing nothing but 8 `unsigned' bit-fields of length 1 would be aligned to a 4 byte boundary and have a size of 4 bytes. By using `-mno-bit-align', the structure would be aligned to a 1 byte boundary and be one byte in size. `-mno-strict-align' `-mstrict-align' On System V.4 and embedded PowerPC systems do not (do) assume that unaligned memory references will be handled by the system. `-mrelocatable' `-mno-relocatable' On embedded PowerPC systems generate code that allows (does not allow) the program to be relocated to a different address at runtime. If you use `-mrelocatable' on any module, all objects linked together must be compiled with `-mrelocatable' or `-mrelocatable-lib'. `-mrelocatable-lib' `-mno-relocatable-lib' On embedded PowerPC systems generate code that allows (does not allow) the program to be relocated to a different address at runtime. Modules compiled with `-mrelocatable-lib' can be linked with either modules compiled without `-mrelocatable' and `-mrelocatable-lib' or with modules compiled with the `-mrelocatable' options. `-mno-toc' `-mtoc' On System V.4 and embedded PowerPC systems do not (do) assume that register 2 contains a pointer to a global area pointing to the addresses used in the program. `-mlittle' `-mlittle-endian' On System V.4 and embedded PowerPC systems compile code for the processor in little endian mode. The `-mlittle-endian' option is the same as `-mlittle'. `-mbig' `-mbig-endian' On System V.4 and embedded PowerPC systems compile code for the processor in big endian mode. The `-mbig-endian' option is the same as `-mbig'. `-mdynamic-no-pic' On Darwin and Mac OS X systems, compile code so that it is not relocatable, but that its external references are relocatable. The resulting code is suitable for applications, but not shared libraries. `-mprioritize-restricted-insns=PRIORITY' This option controls the priority that is assigned to dispatch-slot restricted instructions during the second scheduling pass. The argument PRIORITY takes the value 0/1/2 to assign NO/HIGHEST/SECOND-HIGHEST priority to dispatch slot restricted instructions. `-msched-costly-dep=DEPENDENCE_TYPE' This option controls which dependences are considered costly by the target during instruction scheduling. The argument DEPENDENCE_TYPE takes one of the following values: NO: no dependence is costly, ALL: all dependences are costly, TRUE_STORE_TO_LOAD: a true dependence from store to load is costly, STORE_TO_LOAD: any dependence from store to load is costly, NUMBER: any dependence which latency >= NUMBER is costly. `-minsert-sched-nops=SCHEME' This option controls which nop insertion scheme will be used during the second scheduling pass. The argument SCHEME takes one of the following values: NO: Don't insert nops. PAD: Pad with nops any dispatch group which has vacant issue slots, according to the scheduler's grouping. REGROUP_EXACT: Insert nops to force costly dependent insns into separate groups. Insert exactly as many nops as needed to force an insn to a new group, according to the estimated processor grouping. NUMBER: Insert nops to force costly dependent insns into separate groups. Insert NUMBER nops to force an insn to a new group. `-mcall-sysv' On System V.4 and embedded PowerPC systems compile code using calling conventions that adheres to the March 1995 draft of the System V Application Binary Interface, PowerPC processor supplement. This is the default unless you configured GCC using `powerpc-*-eabiaix'. `-mcall-sysv-eabi' Specify both `-mcall-sysv' and `-meabi' options. `-mcall-sysv-noeabi' Specify both `-mcall-sysv' and `-mno-eabi' options. `-mcall-solaris' On System V.4 and embedded PowerPC systems compile code for the Solaris operating system. `-mcall-linux' On System V.4 and embedded PowerPC systems compile code for the Linux-based GNU system. `-mcall-gnu' On System V.4 and embedded PowerPC systems compile code for the Hurd-based GNU system. `-mcall-netbsd' On System V.4 and embedded PowerPC systems compile code for the NetBSD operating system. `-maix-struct-return' Return all structures in memory (as specified by the AIX ABI). `-msvr4-struct-return' Return structures smaller than 8 bytes in registers (as specified by the SVR4 ABI). `-mabi=ABI-TYPE' Extend the current ABI with a particular extension, or remove such extension. Valid values are ALTIVEC, NO-ALTIVEC, SPE, NO-SPE, IBMLONGDOUBLE, IEEELONGDOUBLE. `-mabi=spe' Extend the current ABI with SPE ABI extensions. This does not change the default ABI, instead it adds the SPE ABI extensions to the current ABI. `-mabi=no-spe' Disable Booke SPE ABI extensions for the current ABI. `-mabi=ibmlongdouble' Change the current ABI to use IBM extended precision long double. This is a PowerPC 32-bit SYSV ABI option. `-mabi=ieeelongdouble' Change the current ABI to use IEEE extended precision long double. *+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~œÜĜŜƜǜȜɜʜ˜̜͜ΜϜМќҜӜԜ՜֜ל؜ٜڜۜܜݜޜߜ  !"#$%&'() This is a PowerPC 32-bit Linux ABI option. `-mprototype' `-mno-prototype' On System V.4 and embedded PowerPC systems assume that all calls to variable argument functions are properly prototyped. Otherwise, the compiler must insert an instruction before every non prototyped call to set or clear bit 6 of the condition code register (CR) to indicate whether floating point values were passed in the floating point registers in case the function takes a variable arguments. With `-mprototype', only calls to prototyped variable argument functions will set or clear the bit. `-msim' On embedded PowerPC systems, assume that the startup module is called `sim-crt0.o' and that the standard C libraries are `libsim.a' and `libc.a'. This is the default for `powerpc-*-eabisim' configurations. `-mmvme' On embedded PowerPC systems, assume that the startup module is called `crt0.o' and the standard C libraries are `libmvme.a' and `libc.a'. `-mads' On embedded PowerPC systems, assume that the startup module is called `crt0.o' and the standard C libraries are `libads.a' and `libc.a'. `-myellowknife' On embedded PowerPC systems, assume that the startup module is called `crt0.o' and the standard C libraries are `libyk.a' and `libc.a'. `-mvxworks' On System V.4 and embedded PowerPC systems, specify that you are compiling for a VxWorks system. `-mwindiss' Specify that you are compiling for the WindISS simulation environment. `-memb' On embedded PowerPC systems, set the PPC_EMB bit in the ELF flags header to indicate that `eabi' extended relocations are used. `-meabi' `-mno-eabi' On System V.4 and embedded PowerPC systems do (do not) adhere to the Embedded Applications Binary Interface (eabi) which is a set of modifications to the System V.4 specifications. Selecting `-meabi' means that the stack is aligned to an 8 byte boundary, a function `__eabi' is called to from `main' to set up the eabi environment, and the `-msdata' option can use both `r2' and `r13' to point to two separate small data areas. Selecting `-mno-eabi' means that the stack is aligned to a 16 byte boundary, do not call an initialization function from `main', and the `-msdata' option will only use `r13' to point to a single small data area. The `-meabi' option is on by default if you configured GCC using one of the `powerpc*-*-eabi*' options. `-msdata=eabi' On System V.4 and embedded PowerPC systems, put small initialized `const' global and static data in the `.sdata2' section, which is pointed to by register `r2'. Put small initialized non-`const' global and static data in the `.sdata' section, which is pointed to by register `r13'. Put small uninitialized global and static data in the `.sbss' section, which is adjacent to the `.sdata' section. The `-msdata=eabi' option is incompatible with the `-mrelocatable' option. The `-msdata=eabi' option also sets the `-memb' option. `-msdata=sysv' On System V.4 and embedded PowerPC systems, put small global and static data in the `.sdata' section, which is pointed to by register `r13'. Put small uninitialized global and static data in the `.sbss' section, which is adjacent to the `.sdata' section. The `-msdata=sysv' option is incompatible with the `-mrelocatable' option. `-msdata=default' `-msdata' On System V.4 and embedded PowerPC systems, if `-meabi' is used, compile code the same as `-msdata=eabi', otherwise compile code the same as `-msdata=sysv'. `-msdata-data' On System V.4 and embedded PowerPC systems, put small global data in the `.sdata' section. Put small uninitialized global data in the `.sbss' section. Do not use register `r13' to address small data however. This is the default behavior unless other `-msdata' options are used. `-msdata=none' `-mno-sdata' On embedded PowerPC systems, put all initialized global and static data in the `.data' section, and all uninitialized data in the `.bss' section. `-G NUM' On embedded PowerPC systems, put global and static items less than or equal to NUM bytes into the small data or bss sections instead of the normal data or bss section. By default, NUM is 8. The `-G NUM' switch is also passed to the linker. All modules should be compiled with the same `-G NUM' value. `-mregnames' `-mno-regnames' On System V.4 and embedded PowerPC systems do (do not) emit register names in the assembly language output using symbolic forms. `-mlongcall' `-mno-longcall' By default assume that all calls are far away so that a longer more expensive calling sequence is required. This is required for calls further than 32 megabytes (33,554,432 bytes) from the current location. A short call will be generated if the compiler knows the call cannot be that far away. This setting can be overridden by the `shortcall' function attribute, or by `#pragma longcall(0)'. Some linkers are capable of detecting out-of-range calls and generating glue code on the fly. On these systems, long calls are unnecessary and generate slower code. As of this writing, the AIX linker can do this, as can the GNU linker for PowerPC/64. It is planned to add this feature to the GNU linker for 32-bit PowerPC systems as well. On Darwin/PPC systems, `#pragma longcall' will generate "jbsr callee, L42", plus a "branch island" (glue code). The two target addresses represent the callee and the "branch island". The Darwin/PPC linker will prefer the first address and generate a "bl callee" if the PPC "bl" instruction will reach the callee directly; otherwise, the linker will generate "bl L42" to call the "branch island". The "branch island" is appended to the body of the calling function; it computes the full 32-bit address of the callee and jumps to it. On Mach-O (Darwin) systems, this option directs the compiler emit to the glue for every direct call, and the Darwin linker decides whether to use or discard it. In the future, we may cause GCC to ignore all longcall specifications when the linker is known to generate glue. `-pthread' Adds support for multithreading with the "pthreads" library. This option sets flags for both the preprocessor and linker.  File: gcc.info, Node: S/390 and zSeries Options, Next: Score Options, Prev: RS/6000 and PowerPC Options, Up: Submodel Options 3.17.28 S/390 and zSeries Options --------------------------------- These are the `-m' options defined for the S/390 and zSeries architecture. `-mhard-float' `-msoft-float' Use (do not use) the hardware floating-point instructions and registers for floating-point operations. When `-msoft-float' is specified, functions in `libgcc.a' will be used to perform floating-point operations. When `-mhard-float' is specified, the compiler generates IEEE floating-point instructions. This is the default. `-mhard-dfp' `-mno-hard-dfp' Use (do not use) the hardware decimal-floating-point instructions for decimal-floating-point operations. When `-mno-hard-dfp' is specified, functions in `libgcc.a' will be used to perform decimal-floating-point operations. When `-mhard-dfp' is specified, the compiler generates decimal-floating-point hardware instructions. This is the default for `-march=z9-ec' or higher. `-mlong-double-64' `-mlong-double-128' These switches control the size of `long double' type. A size of 64bit makes the `long double' type equivalent to the `double' type. This is the default. `-mbackchain' `-mno-backchain' Store (do not store) the address of the caller's frame as backchain pointer into the callee's stack frame. A backchain may be needed to allow debugging using tools that do not understand DWARF-2 call frame information. When `-mno-packed-stack' is in effect, the backchain pointer is stored at the bottom of the stack frame; when `-mpacked-stack' is in effect, the backchain is placed into the topmost word of the 96/160 byte register save area. In general, code compiled with `-mbackchain' is call-compatible with code compiled with `-mmo-backchain'; however, use of the backchain for debugging purposes usually requires that the whole binary is built with `-mbackchain'. Note that the combination of `-mbackchain', `-mpacked-stack' and `-mhard-float' is not supported. In order to build a linux kernel use `-msoft-float'. The default is to not maintain the backchain. `-mpacked-stack' `-mno-packed-stack' Use (do not use) the packed stack layout. When `-mno-packed-stack' is specified, the compiler uses the all fields of the 96/160 byte register save area only for their default purpose; unused fields still take up stack space. When `-mpacked-stack' is specified, register save slots are densely packed at the top of the register save area; unused space is reused for other purposes, allowing for more efficient use of the available stack space. However, when `-mbackchain' is also in effect, the topmost word of the save area is always used to store the backchain, and the return address register is always saved two words below the backchain. As long as the stack frame backchain is not used, code generated with `-mpacked-stack' is call-compatible with code generated with `-mno-packed-stack'. Note that some non-FSF releases of GCC 2.95 for S/390 or zSeries generated code that uses the stack frame backchain at run time, not just for debugging purposes. Such code is not call-compatible with code compiled with `-mpacked-stack'. Also, note that the combination of `-mbackchain', `-mpacked-stack' and `-mhard-float' is not supported. In order to build a linux kernel use `-msoft-float'. The default is to not use the packed stack layout. `-msmall-exec' `-mno-small-exec' Generate (or do not generate) code using the `bras' instruction to do subroutine calls. This only works reliably if the total executable size does not exceed 64k. The default is to use the `basr' instruction instead, which does not have this limitation. `-m64' `-m31' When `-m31' is specified, generate code compliant to the GNU/Linux for S/390 ABI. When `-m64' is specified, generate code compliant to the GNU/Linux for zSeries ABI. This allows GCC in particular to generate 64-bit instructions. For the `s390' targets, the default is `-m31', while the `s390x' targets default to `-m64'. `-mzarch' `-mesa' When `-mzarch' is specified, generate code using the instructions available on z/Architecture. When `-mesa' is specified, generate code using the instructions available on ESA/390. Note that `-mesa' is not possible with `-m64'. When generating code compliant to the GNU/Linux for S/390 ABI, the default is `-mesa'. When generating code compliant to the GNU/Linux for zSeries ABI, the default is `-mzarch'. `-mmvcle' `-mno-mvcle' Generate (or do not generate) code using the `mvcle' instruction to perform block moves. When `-mno-mvcle' is specified, use a `mvc' loop instead. This is the default unless optimizing for size. `-mdebug' `-mno-debug' Print (or do not print) additional debug information when compiling. The default is to not print debug information. `-march=CPU-TYPE' Generate code that will run on CPU-TYPE, which is the name of a system representing a certain processor type. Possible values for CPU-TYPE are `g5', `g6', `z900', `z990', `z9-109' and `z9-ec'. When generating code using the instructions available on z/Architecture, the default is `-march=z900'. Otherwise, the default is `-march=g5'. `-mtune=CPU-TYPE' Tune to CPU-TYPE everything applicable about the generated code, except for the ABI and the set of available instructions. The list of CPU-TYPE values is the same as for `-march'. The default is the value used for `-march'. `-mtpf-trace' `-mno-tpf-trace' Generate code that adds (does not add) in TPF OS specific branches to trace routines in the operating system. This option is off by default, even when compiling for the TPF OS. `-mfused-madd' `-mno-fused-madd' Generate code that uses (does not use) the floating point multiply and accumulate instructions. These instructions are generated by default if hardware floating point is used. `-mwarn-framesize=FRAMESIZE' Emit a warning if the current function exceeds the given frame size. Because this is a compile time check it doesn't need to be a real problem when the program runs. It is intended to identify functions which most probably cause a stack overflow. It is useful to be used in an environment with limited stack size e.g. the linux kernel. `-mwarn-dynamicstack' Emit a warning if the function calls alloca or uses dynamically sized arrays. This is generally a bad idea with a limited stack size. `-mstack-guard=STACK-GUARD' `-mstack-size=STACK-SIZE' If these options are provided the s390 back end emits additional instructions in the function prologue which trigger a trap if the stack size is STACK-GUARD bytes above the STACK-SIZE (remember that the stack on s390 grows downward). If the STACK-GUARD option is omitted the smallest power of 2 larger than the frame size of the compiled function is chosen. These options are intended to be used to help debugging stack overflow problems. The additionally emitted code causes only little overhead and hence can also be used in production like systems without greater performance degradation. The given values have to be exact powers of 2 and STACK-SIZE has to be greater than STACK-GUARD without exceeding 64k. In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by STACK-SIZE. The STACK-GUARD option can only be used in conjunction with STACK-SIZE.  File: gcc.info, Node: Score Options, Next: SH Options, Prev: S/390 and zSeries Options, Up: Submodel Options 3.17.29 Score Options --------------------- These options are defined for Score implementations: `-meb' Compile code for big endian mode. This is the default. `-mel' Compile code for little endian mode. `-mnhwloop' Disable generate bcnz instruction. `-muls' Enable generate unaligned load and store instruction. `-mmac' Enable the use of multiply-accumulate instructions. Disabled by default. `-mscore5' Specify the SCORE5 as the target architecture. `-mscore5u' Specify the SCORE5U of the target architecture. `-mscore7' Specify the SCORE7 as the target architecture. This is the default. `-mscore7d' Specify the SCORE7D as the target architecture.  File: gcc.info, Node: SH Options, Next: SPARC Options, Prev: Score Options, Up: Submodel Options 3.17.30 SH Options ------------------ These `-m' options are defined for the SH implementations: `-m1' Generate code for the SH1. `-m2' Generate code for the SH2. `-m2e' Generate code for the SH2e. `-m3' Generate code for the SH3. `-m3e' Generate code for the SH3e. `-m4-nofpu' Generate code for the SH4 without a floating-point unit. `-m4-single-only' Generate code for the SH4 with a floating-point unit that only supports single-precision arithmetic. `-m4-single' Generate code for the SH4 assuming the floating-point unit is in single-precision mode by default. `-m4' Generate code for the SH4. `-m4a-nofpu' Generate code for the SH4al-dsp, or for a SH4a in such a way that the floating-point unit is not used. `-m4a-single-only' Generate code for the SH4a, in such a way that no double-precision floating point operations are used. `-m4a-single' Generate code for the SH4a assuming the floating-point unit is in single-precision mode by default. `-m4a' Generate code for the SH4a. `-m4al' Same as `-m4a-nofpu', except that it implicitly passes `-dsp' to the assembler. GCC doesn't generate any DSP instructions at the moment. `-mb' Compile code for the processor in big endian mode. `-ml' Compile code for the processor in little endian mode. `-mdalign' Align doubles at 64-bit boundaries. Note that this changes the calling conventions, and thus some functions from the standard C library will not work unless you recompile it first with `-mdalign'. `-mrelax' Shorten some address references at link time, when possible; uses the linker option `-relax'. `-mbigtable' Use 32-bit offsets in `switch' tables. The default is to use 16-bit offsets. `-mfmovd' Enable the use of the instruction `fmovd'. `-mhitachi' Comply with the calling conventions defined by Renesas. `-mrenesas' Comply with the calling conventions defined by Renesas. `-mno-renesas' Comply with the calling conventions defined for GCC before the Renesas conventions were available. This option is the default for all targets of the SH toolchain except for `sh-symbianelf'. `-mnomacsave' Mark the `MAC' register as call-clobbered, even if `-mhitachi' is given. `-mieee' Increase IEEE-compliance of floating-point code. At the moment, this is equivalent to `-fno-finite-math-only'. When generating 16 bit SH opcodes, getting IEEE-conforming results for comparisons of NANs / infinities incurs extra overhead in every floating point comparison, therefore the default is set to `-ffinite-math-only'. `-minline-ic_invalidate' Inline code to invalidate instruction cache entries after setting up nested function trampolines. This option has no effect if -musermode is in effect and the selected code generation option (e.g. -m4) does not allow the use of the icbi instruction. If the selected code generation option does not allow the use of the icbi instruction, and -musermode is not in effect, the inlined code will manipulate the instruction cache address array directly with an associative write. This not only requires privileged mode, but it will also fail if the cache line had been mapped via the TLB and has become unmapped. `-misize' Dump instruction size and location in the assembly code. `-mpadstruct' This option is deprecated. It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI. `-mspace' Optimize for space instead of speed. Implied by `-Os'. `-mprefergot' When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table. `-musermode' Don't generate privileged mode only code; implies -mno-inline-ic_invalidate if the inlined code would not work in user mode. This is the default when the target is `sh-*-linux*'. `-multcost=NUMBER' Set the cost to assume for a multiply insn. `-mdiv=STRATEGY' Set the division strategy to use for SHmedia code. STRATEGY must be one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp . "fp" performs the operation in floating point. This has a very high latency, but needs only a few instructions, so it might be a good choice if your code has enough easily exploitable ILP to allow the compiler to schedule the floating point instructions together with other instructions. Division by zero causes a floating point exception. "inv" uses integer operations to calculate the inverse of the divisor, and then multiplies the dividend with the inverse. This strategy allows cse and hoisting of the inverse calculation. Division by zero calculates an unspecified result, but does not trap. "inv:minlat" is a variant of "inv" where if no cse / hoisting opportunities have been found, or if the entire operation has been hoisted to the same place, the last stages of the inverse calculation are intertwined with the final multiply to reduce the overall latency, at the expense of using a few more instructions, and thus offering fewer scheduling opportunities with other code. "call" calls a library function that usually implements the inv:minlat strategy. This gives high code density for m5-*media-nofpu compilations. "call2" uses a different entry point of the same library function, where it assumes that a pointer to a lookup table has already been set up, which exposes the pointer load to cse / code hoisting optimizations. "inv:call", "inv:call2" and "inv:fp" all use the "inv" algorithm for initial code generation, but if the code stays unoptimized, revert to the "call", "call2", or "fp" strategies, respectively. Note that the potentially-trapping side effect of division by zero is carried by a separate instruction, so it is possible that all the integer instructions are hoisted out, but the marker for the side effect stays where it is. A recombination to fp operations or a call is not possible in that case. "inv20u" and "inv20l" are variants of the "inv:minlat" strategy. In the case that the inverse calculation was nor separated from the multiply, they speed up division where the dividend fits into 20 bits (plus sign where applicable), by inserting a test to skip a number of operations in this case; this test slows down the case of larger dividends. inv20u assumes the case of a such a small dividend to be unlikely, and inv20l assumes it to be likely. `-mdivsi3_libfunc=NAME' Set the name of the library function used for 32 bit signed division to NAME. This only affect the name used in the call and inv:call division strategies, and the compiler will still expect the same sets of input/output/clobbe