B\-mabi=gnu\fR" 4
.IX Item "-mabi=gnu"
.PD
Generate code that passes function parameters and return values that (in
the called function) are seen as registers \f(CW$0\fR and up, as opposed to
the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up.
.IP "\fB\-mzero\-extend\fR" 4
.IX Item "-mzero-extend"
.PD 0
.IP "\fB\-mno\-zero\-extend\fR" 4
.IX Item "-mno-zero-extend"
.PD
When reading data from memory in sizes shorter than 64 bits, use (do not
use) zero-extending load instructions by default, rather than
sign-extending ones.
.IP "\fB\-mknuthdiv\fR" 4
.IX Item "-mknuthdiv"
.PD 0
.IP "\fB\-mno\-knuthdiv\fR" 4
.IX Item "-mno-knuthdiv"
.PD
Make the result of a division yielding a remainder have the same sign as
the divisor.  With the default, \fB\-mno\-knuthdiv\fR, the sign of the
remainder follows the sign of the dividend.  Both methods are
arithmetically valid, the latter being almost exclusively used.
.IP "\fB\-mtoplevel\-symbols\fR" 4
.IX Item "-mtoplevel-symbols"
.PD 0
.IP "\fB\-mno\-toplevel\-symbols\fR" 4
.IX Item "-mno-toplevel-symbols"
.PD
Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly
code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive.
.IP "\fB\-melf\fR" 4
.IX Item "-melf"
Generate an executable in the \s-1ELF\s0 format, rather than the default
\&\fBmmo\fR format used by the \fBmmix\fR simulator.
.IP "\fB\-mbranch\-predict\fR" 4
.IX Item "-mbranch-predict"
.PD 0
.IP "\fB\-mno\-branch\-predict\fR" 4
.IX Item "-mno-branch-predict"
.PD
Use (do not use) the probable-branch instructions, when static branch
prediction indicates a probable branch.
.IP "\fB\-mbase\-addresses\fR" 4
.IX Item "-mbase-addresses"
.PD 0
.IP "\fB\-mno\-base\-addresses\fR" 4
.IX Item "-mno-base-addresses"
.PD
Generate (do not generate) code that uses \fIbase addresses\fR.  Using a
base address automatically generates a request (handled by the assembler
and the linker) for a constant to be set up in a global register.  The
register is used for one or more base address requests within the range 0
to 255 from the value held in the register.  The generally leads to short
and fast code, but the number of different data items that can be
addressed is limited.  This means that a program that uses lots of static
data may require \fB\-mno\-base\-addresses\fR.
.IP "\fB\-msingle\-exit\fR" 4
.IX Item "-msingle-exit"
.PD 0
.IP "\fB\-mno\-single\-exit\fR" 4
.IX Item "-mno-single-exit"
.PD
Force (do not force) generated code to have a single exit point in each
function.
.PP
\fI\s-1MN10300\s0 Options\fR
.IX Subsection "MN10300 Options"
.PP
These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures:
.IP "\fB\-mmult\-bug\fR" 4
.IX Item "-mmult-bug"
Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0
processors.  This is the default.
.IP "\fB\-mno\-mult\-bug\fR" 4
.IX Item "-mno-mult-bug"
Do not generate code to avoid bugs in the multiply instructions for the
\&\s-1MN10300\s0 processors.
.IP "\fB\-mam33\fR" 4
.IX Item "-mam33"
Generate code which uses features specific to the \s-1AM33\s0 processor.
.IP "\fB\-mno\-am33\fR" 4
.IX Item "-mno-am33"
Do not generate code which uses features specific to the \s-1AM33\s0 processor.  This
is the default.
.IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4
.IX Item "-mreturn-pointer-on-d0"
When generating a function which returns a pointer, return the pointer
in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR.  Otherwise, the pointer is returned
only in a0, and attempts to call such functions without a prototype
would result in errors.  Note that this option is on by default; use
\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it.
.IP "\fB\-mno\-crt0\fR" 4
.IX Item "-mno-crt0"
Do not link in the C run-time initialization object file.
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Indicate to the linker that it should perform a relaxation optimization pass
to shorten branches, calls and absolute memory addresses.  This option only
has an effect when used on the command line for the final link step.
.Sp
This option makes symbolic debugging impossible.
.PP
\fI\s-1MT\s0 Options\fR
.IX Subsection "MT Options"
.PP
These \fB\-m\fR options are defined for Morpho \s-1MT\s0 architectures:
.IP "\fB\-march=\fR\fIcpu-type\fR" 4
.IX Item "-march=cpu-type"
Generate code that will run on \fIcpu-type\fR, which is the name of a system
representing a certain processor type.  Possible values for
\&\fIcpu-type\fR are \fBms1\-64\-001\fR, \fBms1\-16\-002\fR,
\&\fBms1\-16\-003\fR and \fBms2\fR.
.Sp
When this option is not used, the default is \fB\-march=ms1\-16\-002\fR.
.IP "\fB\-mbacc\fR" 4
.IX Item "-mbacc"
Use byte loads and stores when generating code.
.IP "\fB\-mno\-bacc\fR" 4
.IX Item "-mno-bacc"
Do not use byte loads and stores when generating code.
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
Use simulator runtime
.IP "\fB\-mno\-crt0\fR" 4
.IX Item "-mno-crt0"
Do not link in the C run-time initialization object file
\&\fIcrti.o\fR.  Other run-time initialization and termination files
such as \fIstartup.o\fR and \fIexit.o\fR are still included on the
linker command line.
.PP
\fI\s-1PDP\-11\s0 Options\fR
.IX Subsection "PDP-11 Options"
.PP
These options are defined for the \s-1PDP\-11:\s0
.IP "\fB\-mfpu\fR" 4
.IX Item "-mfpu"
Use hardware \s-1FPP\s0 floating point.  This is the default.  (\s-1FIS\s0 floating
point on the \s-1PDP\-11/40\s0 is not supported.)
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Do not use hardware floating point.
.IP "\fB\-mac0\fR" 4
.IX Item "-mac0"
Return floating-point results in ac0 (fr0 in Unix assembler syntax).
.IP "\fB\-mno\-ac0\fR" 4
.IX Item "-mno-ac0"
Return floating-point results in memory.  This is the default.
.IP "\fB\-m40\fR" 4
.IX Item "-m40"
Generate code for a \s-1PDP\-11/40\s0.
.IP "\fB\-m45\fR" 4
.IX Item "-m45"
Generate code for a \s-1PDP\-11/45\s0.  This is the default.
.IP "\fB\-m10\fR" 4
.IX Item "-m10"
Generate code for a \s-1PDP\-11/10\s0.
.IP "\fB\-mbcopy\-builtin\fR" 4
.IX Item "-mbcopy-builtin"
Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory.  This is the
default.
.IP "\fB\-mbcopy\fR" 4
.IX Item "-mbcopy"
Do not use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory.
.IP "\fB\-mint16\fR" 4
.IX Item "-mint16"
.PD 0
.IP "\fB\-mno\-int32\fR" 4
.IX Item "-mno-int32"
.PD
Use 16\-bit \f(CW\*(C`int\*(C'\fR.  This is the default.
.IP "\fB\-mint32\fR" 4
.IX Item "-mint32"
.PD 0
.IP "\fB\-mno\-int16\fR" 4
.IX Item "-mno-int16"
.PD
Use 32\-bit \f(CW\*(C`int\*(C'\fR.
.IP "\fB\-mfloat64\fR" 4
.IX Item "-mfloat64"
.PD 0
.IP "\fB\-mno\-float32\fR" 4
.IX Item "-mno-float32"
.PD
Use 64\-bit \f(CW\*(C`float\*(C'\fR.  This is the default.
.IP "\fB\-mfloat32\fR" 4
.IX Item "-mfloat32"
.PD 0
.IP "\fB\-mno\-float64\fR" 4
.IX Item "-mno-float64"
.PD
Use 32\-bit \f(CW\*(C`float\*(C'\fR.
.IP "\fB\-mabshi\fR" 4
.IX Item "-mabshi"
Use \f(CW\*(C`abshi2\*(C'\fR pattern.  This is the default.
.IP "\fB\-mno\-abshi\fR" 4
.IX Item "-mno-abshi"
Do not use \f(CW\*(C`abshi2\*(C'\fR pattern.
.IP "\fB\-mbranch\-expensive\fR" 4
.IX Item "-mbranch-expensive"
Pretend that branches are expensive.  This is for experimenting with
code generation only.
.IP "\fB\-mbranch\-cheap\fR" 4
.IX Item "-mbranch-cheap"
Do not pretend that branches are expensive.  This is the default.
.IP "\fB\-msplit\fR" 4
.IX Item "-msplit"
Generate code for a system with split I&D.
.IP "\fB\-mno\-split\fR" 4
.IX Item "-mno-split"
Generate code for a system without split I&D.  This is the default.
.IP "\fB\-munix\-asm\fR" 4
.IX Item "-munix-asm"
Use Unix assembler syntax.  This is the default when configured for
\&\fBpdp11\-*\-bsd\fR.
.IP "\fB\-mdec\-asm\fR" 4
.IX Item "-mdec-asm"
Use \s-1DEC\s0 assembler syntax.  This is the default when configured for any
\&\s-1PDP\-11\s0 target other than \fBpdp11\-*\-bsd\fR.
.PP
\fIPowerPC Options\fR
.IX Subsection "PowerPC Options"
.PP
These are listed under
.PP
\fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR
.IX Subsection "IBM RS/6000 and PowerPC Options"
.PP
These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC:
.IP "\fB\-mpower\fR" 4
.IX Item "-mpower"
.PD 0
.IP "\fB\-mno\-ÉbÊbËbÌbÍbÎbÏbÐbÑbÒbÓbÔbÕbÖb×bØbÙbÚbÛbÜbÝbÞbßbàbábâbãbäbåbæbçbèbébêbëbìbíbîbïbðbñbòbóbôbõböb÷bøbùbúbûbübýbþbÿbc
cccccccc	c
ccc
ccccccccccccccccccc c!c"c#c$c%c&c'c(c)c*c+c,c-c.c/c0c1c2c3c4c5c6c7c8c9c:c;c<cpower\fR" 4
.IX Item "-mno-power"
.IP "\fB\-mpower2\fR" 4
.IX Item "-mpower2"
.IP "\fB\-mno\-power2\fR" 4
.IX Item "-mno-power2"
.IP "\fB\-mpowerpc\fR" 4
.IX Item "-mpowerpc"
.IP "\fB\-mno\-powerpc\fR" 4
.IX Item "-mno-powerpc"
.IP "\fB\-mpowerpc\-gpopt\fR" 4
.IX Item "-mpowerpc-gpopt"
.IP "\fB\-mno\-powerpc\-gpopt\fR" 4
.IX Item "-mno-powerpc-gpopt"
.IP "\fB\-mpowerpc\-gfxopt\fR" 4
.IX Item "-mpowerpc-gfxopt"
.IP "\fB\-mno\-powerpc\-gfxopt\fR" 4
.IX Item "-mno-powerpc-gfxopt"
.IP "\fB\-mpowerpc64\fR" 4
.IX Item "-mpowerpc64"
.IP "\fB\-mno\-powerpc64\fR" 4
.IX Item "-mno-powerpc64"
.IP "\fB\-mmfcrf\fR" 4
.IX Item "-mmfcrf"
.IP "\fB\-mno\-mfcrf\fR" 4
.IX Item "-mno-mfcrf"
.IP "\fB\-mpopcntb\fR" 4
.IX Item "-mpopcntb"
.IP "\fB\-mno\-popcntb\fR" 4
.IX Item "-mno-popcntb"
.IP "\fB\-mfprnd\fR" 4
.IX Item "-mfprnd"
.IP "\fB\-mno\-fprnd\fR" 4
.IX Item "-mno-fprnd"
.IP "\fB\-mcmpb\fR" 4
.IX Item "-mcmpb"
.IP "\fB\-mno\-cmpb\fR" 4
.IX Item "-mno-cmpb"
.IP "\fB\-mmfpgpr\fR" 4
.IX Item "-mmfpgpr"
.IP "\fB\-mno\-mfpgpr\fR" 4
.IX Item "-mno-mfpgpr"
.IP "\fB\-mhard\-dfp\fR" 4
.IX Item "-mhard-dfp"
.IP "\fB\-mno\-hard\-dfp\fR" 4
.IX Item "-mno-hard-dfp"
.PD
\&\s-1GCC\s0 supports two related instruction set architectures for the
\&\s-1RS/6000\s0 and PowerPC.  The \fI\s-1POWER\s0\fR instruction set are those
instructions supported by the \fBrios\fR chip set used in the original
\&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the
architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
the \s-1IBM\s0 4xx, 6xx, and follow-on microprocessors.
.Sp
Neither architecture is a subset of the other.  However there is a
large common subset of instructions supported by both.  An \s-1MQ\s0
register is included in processors supporting the \s-1POWER\s0 architecture.
.Sp
You use these options to specify which instructions are available on the
processor you are using.  The default value of these options is
determined when configuring \s-1GCC\s0.  Specifying the
\&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these
options.  We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option
rather than the options listed above.
.Sp
The \fB\-mpower\fR option allows \s-1GCC\s0 to generate instructions that
are found only in the \s-1POWER\s0 architecture and to use the \s-1MQ\s0 register.
Specifying \fB\-mpower2\fR implies \fB\-power\fR and also allows \s-1GCC\s0
to generate instructions that are present in the \s-1POWER2\s0 architecture but
not the original \s-1POWER\s0 architecture.
.Sp
The \fB\-mpowerpc\fR option allows \s-1GCC\s0 to generate instructions that
are found only in the 32\-bit subset of the PowerPC architecture.
Specifying \fB\-mpowerpc\-gpopt\fR implies \fB\-mpowerpc\fR and also allows
\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the
General Purpose group, including floating-point square root.  Specifying
\&\fB\-mpowerpc\-gfxopt\fR implies \fB\-mpowerpc\fR and also allows \s-1GCC\s0 to
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
.Sp
The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from
condition register field instruction implemented on the \s-1POWER4\s0
processor and other processors that support the PowerPC V2.01
architecture.
The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and
double precision \s-1FP\s0 reciprocal estimate instruction implemented on the
\&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02
architecture.
The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to
integer instructions implemented on the \s-1POWER5+\s0 processor and other
processors that support the PowerPC V2.03 architecture.
The \fB\-mcmpb\fR option allows \s-1GCC\s0 to generate the compare bytes
instruction implemented on the \s-1POWER6\s0 processor and other processors
that support the PowerPC V2.05 architecture.
The \fB\-mmfpgpr\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 move to/from
general purpose register instructions implemented on the \s-1POWER6X\s0
processor and other processors that support the extended PowerPC V2.05
architecture.
The \fB\-mhard\-dfp\fR option allows \s-1GCC\s0 to generate the decimal floating
point instructions implemented on some \s-1POWER\s0 processors.
.Sp
The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional
64\-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64\-bit, doubleword quantities.  \s-1GCC\s0 defaults to
\&\fB\-mno\-powerpc64\fR.
.Sp
If you specify both \fB\-mno\-power\fR and \fB\-mno\-powerpc\fR, \s-1GCC\s0
will use only the instructions in the common subset of both
architectures plus some special \s-1AIX\s0 common-mode calls, and will not use
the \s-1MQ\s0 register.  Specifying both \fB\-mpower\fR and \fB\-mpowerpc\fR
permits \s-1GCC\s0 to use any instruction from either architecture and to
allow use of the \s-1MQ\s0 register; specify this for the Motorola \s-1MPC601\s0.
.IP "\fB\-mnew\-mnemonics\fR" 4
.IX Item "-mnew-mnemonics"
.PD 0
.IP "\fB\-mold\-mnemonics\fR" 4
.IX Item "-mold-mnemonics"
.PD
Select which mnemonics to use in the generated assembler code.  With
\&\fB\-mnew\-mnemonics\fR, \s-1GCC\s0 uses the assembler mnemonics defined for
the PowerPC architecture.  With \fB\-mold\-mnemonics\fR it uses the
assembler mnemonics defined for the \s-1POWER\s0 architecture.  Instructions
defined in only one architecture have only one mnemonic; \s-1GCC\s0 uses that
mnemonic irrespective of which of these options is specified.
.Sp
\&\s-1GCC\s0 defaults to the mnemonics appropriate for the architecture in
use.  Specifying \fB\-mcpu=\fR\fIcpu_type\fR sometimes overrides the
value of these option.  Unless you are building a cross-compiler, you
should normally not specify either \fB\-mnew\-mnemonics\fR or
\&\fB\-mold\-mnemonics\fR, but should instead accept the default.
.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set architecture type, register usage, choice of mnemonics, and
instruction scheduling parameters for machine type \fIcpu_type\fR.
Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR,
\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB505\fR,
\&\fB601\fR, \fB602\fR, \fB603\fR, \fB603e\fR, \fB604\fR,
\&\fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, \fB7400\fR,
\&\fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR,
\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBec603e\fR, \fBG3\fR,
\&\fBG4\fR, \fBG5\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR,
\&\fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \fBpower6\fR,
\&\fBpower6x\fR, \fBcommon\fR, \fBpowerpc\fR, \fBpowerpc64\fR,
\&\fBrios\fR, \fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64\fR.
.Sp
\&\fB\-mcpu=common\fR selects a completely generic processor.  Code
generated under this option will run on any \s-1POWER\s0 or PowerPC processor.
\&\s-1GCC\s0 will use only the instructions in the common subset of both
architectures, and will not use the \s-1MQ\s0 register.  \s-1GCC\s0 assumes a generic
processor model for scheduling purposes.
.Sp
\&\fB\-mcpu=power\fR, \fB\-mcpu=power2\fR, \fB\-mcpu=powerpc\fR, and
\&\fB\-mcpu=powerpc64\fR specify generic \s-1POWER\s0, \s-1POWER2\s0, pure 32\-bit
PowerPC (i.e., not \s-1MPC601\s0), and 64\-bit PowerPC architecture machine
types, with an appropriate, generic processor model assumed for
scheduling purposes.
.Sp
The other options specify a specific processor.  Code generated under
those options will run best on that processor, and may not run at all on
others.
.Sp
The \fB\-mcpu\fR options automatically enable or disable the
following options:
.Sp
\&\fB\-maltivec  \-mfprnd  \-mhard\-float  \-mmfcrf  \-mmultiple 
\&\-mnew\-mnemonics  \-mpopcntb  \-mpower  \-mpower2  \-mpowerpc64 
\&\-mpowerpc\-gpopt  \-mpowerpc\-gfxopt  \-mstring  \-mmulhw  \-mdlmzb  \-mmfpgpr\fR
.Sp
The particular options set for any particular \s-1CPU\s0 will vary between
compiler versions, depending on what setting seems to produce optimal
code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's
capabilities.  If you wish to set an individual option to a particular
value, you may specify it after the \fB\-mcpu\fR option, like
\&\fB\-mcpu=970 \-mno\-altivec\fR.
.Sp
On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are
not enabled or disabled by the \fB\-mcpu\fR option at present because
\&\s-1AIX\s0 does not have full support for these options.  You may still
enable or disable them individually if you're sure it'll work in your
environment.
.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set the instruction scheduling parameters for machine type
\&\fIcpu_type\fR, but do not set the architecture type, register usage, or
choice of mnemonics, as \fB\-mcpu=\fR\fIcpu_type\fR would.  The same
values for \fIcpu_type\fR are used for \fB\-mtune\fR as for
\&\fB\-mcpu\fR.  If both are specified, the code generated will use the
architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the
scheduling parameters set by \fB\-mtune\fR.
.IP "\fB\-mswdiv\fR" 4
.IX Item "-mswdiv"
.PD 0
.IP "\fB\-mno\-swdiv\fR" 4
.IX Item "-mno-swdiv"
.PD
Generate code to compute division as reciprocal estimate and iterative
refinement, creating opportunities for increased throughput.  This
feature requires: optional PowerPC Graphics instruction set for single
precision and \s-1FRE\s0 instruction for double precision, assuming divides
cannot generate user-visible traps, and the domain values not include
Infinities, denormals or zero denominator.
.IP "\fB\-maltivec\fR" 4
.IX Item "-maltivec"
.PD 0
.IP "\fB\-mno\-altivec\fR" 4
.IX Item "-mno-altivec"
.PD
Generate code that uses (does not use) AltiVec instructions, and also
enable the use of built-in functions that allow more direct access to
the AltiVec instruction set.  You may also need to set
\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0
enhancements.
.IP "\fB\-mvrsave\fR" 4
.IX Item "-mvrsave"
.PD 0
.IP "\fB\-mno\-vrsave\fR" 4
.IX Item "-mno-vrsave"
.PD
Generate \s-1VRSAVE\s0 instructions when generating AltiVec code.
.IP "\fB\-msecure\-plt\fR" 4
.IX Item "-msecure-plt"
Generate code that allows ld and ld.so to build executables and shared
libraries with non-exec .plt and .got sections.  This is a PowerPC
32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-mbss\-plt\fR" 4
.IX Item "-mbss-plt"
Generate code that uses a \s-1BSS\s0 .plt section that ld.so fills in, and
requires .plt and .got sections that are both writable and executable.
This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-misel\fR" 4
.IX Item "-misel"
.PD 0
.IP "\fB\-mno\-isel\fR" 4
.IX Item "-mno-isel"
.PD
This switch enables or disables the generation of \s-1ISEL\s0 instructions.
.IP "\fB\-misel=\fR\fIyes/no\fR" 4
.IX Item "-misel=yes/no"
This switch has been deprecated.  Use \fB\-misel\fR and
\&\fB\-mno\-isel\fR instead.
.IP "\fB\-mspe\fR" 4
.IX Item "-mspe"
.PD 0
.IP "\fB\-mno\-spe\fR" 4
.IX Item "-mno-spe"
.PD
This switch enables or disables the generation of \s-1SPE\s0 simd
instructions.
.IP "\fB\-mpaired\fR" 4
.IX Item "-mpaired"
.PD 0
.IP "\fB\-mno\-paired\fR" 4
.IX Item "-mno-paired"
.PD
This switch enables or disables the generation of \s-1PAIRED\s0 simd
instructions.
.IP "\fB\-mspe=\fR\fIyes/no\fR" 4
.IX Item "-mspe=yes/no"
This option has been deprecated.  Use \fB\-mspe\fR and
\&\fB\-mno\-spe\fR instead.
.IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4
.IX Item "-mfloat-gprs=yes/single/double/no"
.PD 0
.IP "\fB\-mfloat\-gprs\fR" 4
.IX Item "-mfloat-gprs"
.PD
This switch enables or disables the generation of floating point
operations on the general purpose registers for architectures that
support it.
.Sp
The argument \fIyes\fR or \fIsingle\fR enables the use of
single-precision floating point operations.
.Sp
The argument \fIdouble\fR enables the use of single and
double-precision floating point operations.
.Sp
The argument \fIno\fR disables floating point operations on the
general purpose registers.
.Sp
This option is currently only available on the MPC854x.
.IP "\fB\-m32\fR" 4
.IX Item "-m32"
.PD 0
.IP "\fB\-m64\fR" 4
.IX Item "-m64"
.PD
Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0
targets (including GNU/Linux).  The 32\-bit environment sets int, long
and pointer to 32 bits and generates code that runs on any PowerPC
variant.  The 64\-bit environment sets int to 32 bits and long and
pointer to 64 bits, and generates code for PowerPC64, as for
\&\fB\-mpowerpc64\fR.
.IP "\fB\-mfull\-toc\fR" 4
.IX Item "-mfull-toc"
.PD 0
.IP "\fB\-mno\-fp\-in\-toc\fR" 4
.IX Item "-mno-fp-in-toc"
.IP "\fB\-mno\-sum\-in\-toc\fR" 4
.IX Item "-mno-sum-in-toc"
.IP "\fB\-mminimal\-toc\fR" 4
.IX Item "-mminimal-toc"
.PD
Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for
every executable file.  The \fB\-mfull\-toc\fR option is selected by
default.  In that case, \s-1GCC\s0 will allocate at least one \s-1TOC\s0 entry for
each unique non-automatic variable reference in your program.  \s-1GCC\s0
will also place floating-point constants in the \s-1TOC\s0.  However, only
16,384 entries are available in the \s-1TOC\s0.
.Sp
If you receive a linker error message that saying you have overflowed
the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used
with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options.
\&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point
constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to
generate code to calculate the sum of an address and a constant at
run-time instead of putting that sum into the \s-1TOC\s0.  You may specify one
or both of these options.  Each causes \s-1GCC\s0 to produce very slightly
slower and larger code at the expense of conserving \s-1TOC\s0 space.
.Sp
If you still run out of space in the \s-1TOC\s0 even when you specify both of
these options, specify \fB\-mminimal\-toc\fR instead.  This option causes
\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file.  When you specify this
option, \s-1GCC\s0 will produce code that is slower and larger but which
uses extremely little \s-1TOC\s0 space.  You may wish to use this option
only on files that contain less frequently executed code.
.IP "\fB\-maix64\fR" 4
.IX Item "-maix64"
.PD 0
.IP "\fB\-maix32\fR" 4
.IX Item "-maix32"
.PD
Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit
\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them.
Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR and
\&\fB\-mpowerpc\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and
implies \fB\-mno\-powerpc64\fR.  \s-1GCC\s0 defaults to \fB\-maix32\fR.
.IP "\fB\-mxl\-compat\fR" 4
.IX Item "-mxl-compat"
.PD 0
.IP "\fB\-mno\-xl\-compat\fR" 4
.IX Item "-mno-xl-compat"
.PD
Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics
when using AIX-compatible \s-1ABI\s0.  Pass floating-point arguments to
prototyped functions beyond the register save area (\s-1RSA\s0) on the stack
in addition to argument FPRs.  Do not assume that most significant
double in 128\-bit long double value is properly rounded when comparing
values and converting to double.  Use \s-1XL\s0 symbol names for long double
support routines.
.Sp
The \s-1AIX\s0 calling convention was extended but not initially documented to
handle an obscure K&R C case of calling a function that takes the
address of its arguments with fewer arguments than declared.  \s-1IBM\s0 \s-1XL\s0
compilers access floating point arguments which do not fit in the
\&\s-1RSA\s0 from the stack when a subroutine is compiled without
optimization.  Because always storing floating-point arguments on the
stack is inefficient and rarely needed, this option is not enabled by
default and only is necessary when calling subroutines compiled by \s-1IBM\s0
\&\s-1XL\s0 compilers without optimization.
.IP "\fB\-mpe\fR" 4
.IX Item "-mpe"
Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0).  Link an
application written to use message passing with special startup code to
enable the application to run.  The system must have \s-1PE\s0 installed in the
standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file
must be overridden with the \fB\-specs=\fR option to specify the
appropriate directory location.  The Parallel Environment does not
support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR
option are incompatible.
.IP "\fB\-malign\-natural\fR" 4
.IX Item "-malign-natural"
.PD 0
.IP "\fB\-malign\-power\fR" 4
.IX Item "-malign-power"
.PD
On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option
\&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger
types, such as floating-point doubles, on their natural size-based boundary.
The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified
alignment rules.  \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0.
.Sp
On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR
is not supported.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
.PD 0
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
.PD
Generate code that does not use (uses) the floating-point register set.
Software floating point emulation is provided if you use the
\&\fB\-msoft\-float\fR option, and pass the option to \s-1GCC\s0 when linking.
.IP "\fB\-mmultiple\fR" 4
.IX Item "-mmultiple"
.PD 0
.IP "\fB\-mno\-multiple\fR" 4
.IX Item "-mno-multiple"
.PD
Generate code that uses (does not use) the load multiple word
instructions and the store multiple word instructions.  These
instructions are generated by default on \s-1POWER\s0 systems, and not
generated on PowerPC systems.  Do not use \fB\-mmultiple\fR on little
endian PowerPC systems, since those instructions do not work when the
processor is in little endian mode.  The exceptions are \s-1PPC740\s0 and
\&\s-1PPC750\s0 which permit the instructions usage in little endian mode.
.IP "\fB\-mstring\fR" 4
.IX Item "-mstring"
.PD 0
.IP "\fB\-mno\-string\fR" 4
.IX Item "-mno-string"
.PD
Generate code that uses (does not use) the load string instructions
and the store string word instructions to save multiple registers and
do small block moves.  These instructions are generated by default on
\&\s-1POWER\s0 systems, and not generated on PowerPC systems.  Do not use
\&\fB\-mstring\fR on little endian PowerPC systems, since those
instructions do not work when the processor is in little endian mode.
The exceptions are \s-1PPC740\s0 and \s-1PPC750\s0 which permit the instructions
usage in little endian mode.
.IP "\fB\-mupdate\fR" 4
.IX Item "-mupdate"
.PD 0
.IP "\fB\-mno\-update\fR" 4
.IX Item "-mno-update"
.PD
Generate code that uses (does not use) the load or store instructions
that update the base register to the address of the calculated memory
location.  These instructions are generated by default.  If you use
\&\fB\-mno\-update\fR, there is a small window between the time that the
stack pointer is updated and the address of the previous frame is
stored, which means code that walks the stack frame across interrupts or
signals may get corrupted data.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mno\-fused\-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Generate code that uses (does not use) the floating point multiply and
accumulate instructions.  These instructions are generated by default if
hardware floating is used.
.IP "\fB\-mmulhw\fR" 4
.IX Item "-mmulhw"
.PD 0
.IP "\fB\-mno\-mulhw\fR" 4
.IX Item "-mno-mulhw"
.PD
Generate code that uses (does not use) the half-word multiply and
multiply-accumulate instructions on the \s-1IBM\s0 405 and 440 processors.
These instructions are generated by default when targetting those
processors.
.IP "\fB\-mdlmzb\fR" 4
.IX Item "-mdlmzb"
.PD 0
.IP "\fB\-mno\-dlmzb\fR" 4
.IX Item "-mno-dlmzb"
.PD
Generate code that uses (does not use) the string-search \fBdlmzb\fR
instruction on the \s-1IBM\s0 405 and 440 processors.  This instruction is
generated by default when targetting those processors.
.IP "\fB\-mno\-bit\-align\fR" 4
.IX Item "-mno-bit-align"
.PD 0
.IP "\fB\-mbit\-align\fR" 4
.IX Item "-mbit-align"
.PD
On System V.4 and embedded PowerPC systems do not (do) force structures
and unions that contain bit-fields to be aligned to the base type of the
bit-field.
.Sp
For example, by default a structure containing nothing but 8
\&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 would be aligned to a 4 byte
boundary and have a size of 4 bytes.  By using \fB\-mno\-bit\-align\fR,
the structure would be aligned to a 1 byte boundary and be one byte in
size.
.IP "\fB\-mno\-strict\-align\fR" 4
.IX Item "-mno-strict-align"
.PD 0
.IP "\fB\-mstrict\-align\fR" 4
.IX Item "-mstrict-align"
.PD
On System V.4 and embedded PowerPC systems do not (do) assume that
unaligned memory references will be handled by the system.
.IP "\fB\-mrelocatable\fR" 4
.IX Item "-mrelocatable"
.PD 0
.IP "\fB\-mno\-relocatable\fR" 4
.IX Item "-mno-relocatable"
.PD
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime.  If you
use \fB\-mrelocatable\fR on any module, all objects linked together must
be compiled with \fB\-mrelocatable\fR or \fB\-mrelocatable\-lib\fR.
.IP "\fB\-mrelocatable\-lib\fR" 4
.IX Item "-mrelocatable-lib"
.PD 0
.IP "\fB\-mno\-relocatable\-lib\fR" 4
.IX Item "-mno-relocatable-lib"
.PD
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime.  Modules
compiled with \fB\-mrelocatable\-lib\fR can be linked with either modules
compiled without \fB\-mrelocatable\fR and \fB\-mrelocatable\-lib\fR or
with modules compiled with the \fB\-mrelocatable\fR options.
.IP "\fB\-mno\-toc\fR" 4
.IX Item "-mno-toc"
.PD 0
.IP "\fB\-mtoc\fR" 4
.IX Item "-mtoc"
.PD
On System V.4 and embedded PowerPC systems do not (do) assume that
register 2 contains a pointer to a global area pointing to the addresses
used in the program.
.IP "\fB\-mlittle\fR" 4
.IX Item "-mlittle"
.PD 0
.IP "\fB\-mlittle\-endian\fR" 4
.IX Item "-mlittle-endian"
.PD
On System V.4 and embedded PowerPC systems compile code for the
processor in little endian mode.  The \fB\-mlittle\-endian\fR option is
the same as \fB\-mlittle\fR.
.IP "\fB\-mbig\fR" 4
.IX Item "-mbig"
.PD 0
.IP "\fB\-mbig\-endian\fR" 4
.IX Item "-mbig-endian"
.PD
On System V.4 and embedded PowerPC systems compile code for the
processor in big endian mode.  The \fB\-mbig\-endian\fR option is
the same as \fB\-mbig\fR.
.IP "\fB\-mdynamic\-no\-pic\fR" 4
.IX Item "-mdynamic-no-pic"
On Darwin and Mac \s-1OS\s0 X systems, compile code so that it is not
relocatable, but that its external references are relocatable.  The
resulting code is suitable for applications, but not shared
libraries.
.IP "\fB\-mprioritize\-restricted\-insns=\fR\fIpriority\fR" 4
.IX Item "-mprioritize-restricted-insns=priority"
This option controls the priority that is assigned to
dispatch-slot restricted instructions during the second scheduling
pass.  The argument \fIpriority\fR takes the value \fI0/1/2\fR to assign
\&\fIno/highest/second\-highest\fR priority to dispatch slot restricted
instructions.
.IP "\fB\-msched\-costly\-dep=\fR\fIdependence_type\fR" 4
.IX Item "-msched-costly-dep=dependence_type"
This option controls which dependences are considered costly
by the target during instruction scheduling.  The argument
\&\fIdependence_type\fR takes one of the following values:
\&\fIno\fR: no dependence is costly,
\&\fIall\fR: all dependences are costly,
\&\fItrue_store_to_load\fR: a true dependence from store to load is costly,
\&\fIstore_to_load\fR: any dependence from store to load is costly,
\&\fInumber\fR: any dependence which latency >= \fInumber\fR is costly.
.IP "\fB\-minsert\-sched\-nops=\fR\fIscheme\fR" 4
.IX Item "-minsert-sched-nops=scheme"
This option controls which nop insertion scheme will be used during
the second scheduling pass.  The argument \fIscheme\fR takes one of the
following values:
\&\fIno\fR: Don't insert nops.
\&\fIpad\fR: Pad with nops any dispatch group which has vacant issue slots,
according to the scheduler's grouping.
\&\fIregroup_exact\fR: Insert nops to force costly dependent insns into
separate groups.  Insert exactly as many nops as needed to force an insn
to a new group, according to the estimated processor grouping.
\&\fInumber\fR: Insert nops to force costly dependent insns into
separate groups.  Insert \fInumber\fR nops to force an insn to a new group.
.IP "\fB\-mcall\-sysv\fR" 4
.IX Item "-mcall-sysv"
On System V.4 and embedded PowerPC systems compile code using calling
conventions that adheres to the March 1995 draft of the System V
Application Binary Interface, PowerPC processor supplement.  This is the
default unless you configured \s-1GCC\s0 using \fBpowerpc\-*\-eabiaix\fR.
.IP "\fB\-mcall\-sysv\-eabi\fR" 4
.IX Item "-mcall-sysv-eabi"
Specify both \fB\-mcall\-sysv\fR and \fB\-meabi\fR options.
.IP "\fB\-mcall\-sysv\-noeabi\fR" 4
.IX Item "-mcall-sysv-noeabi"
Specify both \fB\-mcall\-sysv\fR and \fB\-mno\-eabi\fR options.
.IP "\fB\-mcall\-solaris\fR" 4
.IX Item "-mcall-solaris"
On System V.4 and embedded PowerPC systems compile code for the Solaris
operating system.
.IP "\fB\-mcall\-linux\fR" 4
.IX Item "-mcall-linux"
On System V.4 and embedded PowerPC systems compile code for the
Linux-based \s-1GNU\s0 system.
.IP "\fB\-mcall\-gnu\fR" 4
.IX Item "-mcall-gnu"
On System V.4 and embedded PowerPC systems compile code for the
Hurd-based \s-1GNU\s0 system.
.IP "\fB\-mcall\-netbsd\fR" 4
.IX Item "-mcall-netbsd"
On System V.4 and embedded PowerPC systems compile code for the
NetBSD operating system.
.IP "\fB\-maix\-struct\-return\fR" 4
.IX Item "-maix-struct-return"
Return all structures in memory (as specified by the \s-1AIX\s0 \s-1ABI\s0).
.IP "\fB\-msvr4\-struct\-return\fR" 4
.IX Item "-msvr4-struct-return"
Return structures smaller than 8 bytes in registers (as specified by the
\&\s-1SVR4\s0 \s-1ABI\s0).
.IP "\fB\-mabi=\fR\fIabi-type\fR" 4
.IX Item "-mabi=abi-type"
Extend the current \s-1ABI\s0 with a particular extension, or remove such extension.
Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR,
\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR.
.IP "\fB\-mabi=spe\fR" 4
.IX Item "-mabi=spe"
Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions.  This does not change
the default \s-1ABI\s0, instead it adds the \s-1SPE\s0 \s-1ABI\s0 extensions to the current
\&\s-1ABI\s0.
.IP "\fB\-mabi=no\-spe\fR" 4
.IX Item "-mabi=no-spe"
Disable Booke \s-1SPE\s0 \s-1ABI\s0 extensions for the current \s-1ABI\s0.
.IP "\fB\-mabi=ibmlongdouble\fR" 4
.IX Item "-mabi=ibmlongdouble"
Change the current \s-1ABI\s0 to use \s-1IBM\s0 extended precision long double.
This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-mabi=ieeelongdouble\fR" 4
.IX Item "-mabi=ieeelongdouble"
Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended precision long double.
This is a PowerPC 32\-bit Linux \s-1ABI\s0 option.
.IP "\fB\-mprototype\fR" 4
.IX Item "-mprototype"
.PD 0
.IP "\fB\-mno\-prototype\fR" 4
.IX Item "-mno-prototype"
.PD
On System V.4 and embedded PowerPC systems assume that all calls to
variable argument functions are properly prototyped.  Otherwise, the
compiler must insert an instruction before every non prototyped call to
set or clear bit 6 of the condition code register (\fI\s-1CR\s0\fR) to
indicate whether floating point values were passed in the floating point
registers in case the function takes a variable arguments.  With
\&\fB\-mprototype\fR, only calls to prototyped variable argument functions
will set or clear the bit.
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
On embedded PowerPC systems, assume that the startup module is called
\&\fIsim\-crt0.o\fR and that the standard C libraries are \fIlibsim.a\fR and
\&\fIlibc.a\fR.  This is the default for \fBpowerpc\-*\-eabisim\fR
configurations.
.IP "\fB\-mmvme\fR" 4
.IX Item "-mmvme"
On embedded PowerPC systems, assume that the startup module is called
\&\fIcrt0.o\fR and the standard C libraries are \fIlibmvme.a\fR and
\&\fIlibc.a\fR.
.IP "\fB\-mads\fR" 4
.IX Item "-mads"
On embedded PowerPC systems, assume that the startup module is called
\&\fIcrt0.o\fR and the standard C libraries are \fIlibads.a\fR and
\&\fIlibc.a\fR.
.IP "\fB\-myellowknife\fR" 4
.IX Item "-myellowknife"
On embedded PowerPC systems, assume that the startup module is called
\&\fIcrt0.o\fR and the standard C libraries are \fIlibyk.a\fR and
\&\fIlibc.a\fR.
.IP "\fB\-mvxworks\fR" 4
.IX Item "-mvxworks"
On System V.4 and embedded PowerPC systems, specify that you are
compiling for a VxWorks system.
.IP "\fB\-mwindiss\fR" 4
.IX Item "-mwindiss"
Specify that you are compiling for the WindISS simulation environment.
.IP "\fB\-memb\fR" 4
.IX Item "-memb"
On embedded PowerPC systems, set the \fI\s-1PPC_EMB\s0\fR bit in the \s-1ELF\s0 flags
header to indicate that \fBeabi\fR extended relocations are used.
.IP "\fB\-meabi\fR" 4
.IX Item "-meabi"
.PD 0
.IP "\fB\-mno\-eabi\fR" 4
.IX Item "-mno-eabi"
.PD
On System V.4 and embedded PowerPC systems do (do not) adhere to the
Embedded Applications Binary Interface (eabi) which is a set of
modifications to the System V.4 specifications.  Selecting \fB\-meabi\fR
means that the stack is aligned to an 8 byte boundary, a function
\&\f(CW\*(C`_\|_eabi\*(C'\fR is called to from \f(CW\*(C`main\*(C'\fR to set up the eabi
environment, and the \fB\-msdata\fR option can use both \f(CW\*(C`r2\*(C'\fR and
\&\f(CW\*(C`r13\*(C'\fR to point to two separate small data areas.  Selecting
\&\fB\-mno\-eabi\fR means that the stack is aligned to a 16 byte boundary,
do not call an initialization function from \f(CW\*(C`main\*(C'\fR, and the
\&\fB\-msdata\fR option will only use \f(CW\*(C`r13\*(C'\fR to point to a single
small data area.  The \fB\-meabi\fR option is on by default if you
configured \s-1GCC\s0 using one of the \fBpowerpc*\-*\-eabi*\fR options.
.IP "\fB\-msdata=eabi\fR" 4
.IX Item "-msdata=eabi"
On System V.4 and embedded PowerPC systems, put small initialized
\&\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata2\fR section, which
is pointed to by register \f(CW\*(C`r2\*(C'\fR.  Put small initialized
non\-\f(CW\*(C`const\*(C'\fR global and static data in the \fB.sdata\fR section,
which is pointed to by register \f(CW\*(C`r13\*(C'\fR.  Put small uninitialized
global and static data in the \fB.sbss\fR section, which is adjacent to
the \fB.sdata\fR section.  The \fB\-msdata=eabi\fR option is
incompatible with the \fB\-mrelocatable\fR option.  The
\&\fB\-msdata=eabi\fR option also sets the \fB\-memb\fR option.
.IP "\fB\-msdata=sysv\fR" 4
.IX Item "-msdata=sysv"
On System V.4 and embedded PowerPC systems, put small global and static
data in the \fB.sdata\fR section, which is pointed to by register
\&\f(CW\*(C`r13\*(C'\fR.  Put small uninitialized global and static data in the
\&\fB.sbss\fR section, which is adjacent to the \fB.sdata\fR section.
The \fB\-msdata=sysv\fR option is incompatible with the
\&\fB\-mrelocatable\fR option.
.IP "\fB\-msdata=default\fR" 4
.IX Item "-msdata=default"
.PD 0
.IP "\fB\-msdata\fR" 4
.IX Item "-msdata"
.PD
On System V.4 and embedded PowerPC systems, if \fB\-meabi\fR is used,
compile code the same as \fB\-msdata=eabi\fR, otherwise compile code the
same as \fB\-msdata=sysv\fR.
.IP "\fB\-msdata\-data\fR" 4
.IX Item "-msdata-data"
On System V.4 and embedded PowerPC systems, put small global
data in the \fB.sdata\fR section.  Put small uninitialized global
data in the \fB.sbss\fR section.  Do not use register \f(CW\*(C`r13\*(C'\fR
to address small data however.  This is the default behavior unless
other \fB\-msdata\fR options are used.
.IP "\fB\-msdata=none\fR" 4
.IX Item "-msdata=none"
.PD 0
.IP "\fB\-mno\-sdata\fR" 4
.IX Item "-mno-sdata"
.PD
On embedded PowerPC systems, put all initialized global and static data
in the \fB.data\fR section, and all uninitialized data in the
\&\fB.bss\fR section.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
On embedded PowerPC systems, put global and static items less than or
equal to \fInum\fR bytes into the small data or bss sections instead of
the normal data or bss section.  By default, \fInum\fR is 8.  The
\&\fB\-G\fR \fInum\fR switch is also passed to the linker.
All modules should be compiled with the same \fB\-G\fR \fInum\fR value.
.IP "\fB\-mregnames\fR" 4
.IX Item "-mregnames"
.PD 0
.IP "\fB\-mno\-regnames\fR" 4
.IX Item "-mno-regnames"
.PD
On System V.4 and embedded PowerPC systems do (do not) emit register
names in the assembly language output using symbolic forms.
.IP "\fB\-mlongcall\fR" 4
.IX Item "-mlongcall"
.PD 0
.IP "\fB\-mno\-longcall\fR" 4
.IX Item "-mno-longcall"
.PD
By default assume that all calls are far away so that a longer more
expensive calling sequence is required.  This is required for calls
further than 32 megabytes (33,554,432 bytes) from the current location.
A short call will be generated if the compiler knows
the call cannot be that far away.  This setting can be overridden by
the \f(CW\*(C`shortcall\*(C'\fR function attribute, or by \f(CW\*(C`#pragma
longcall(0)\*(C'\fR.
.Sp
Some linkers are capable of detecting out-of-range calls and generating
glue code on the fly.  On these systems, long calls are unnecessary and
generate slower code.  As of this writing, the \s-1AIX\s0 linker can do this,
as can the \s-1GNU\s0 linker for PowerPC/64.  It is planned to add this feature
to the \s-1GNU\s0 linker for 32\-bit PowerPC systems as well.
.Sp
On Darwin/PPC systems, \f(CW\*(C`#pragma longcall\*(C'\fR will generate \*(L"jbsr
callee, L42\*(R", plus a \*(L"branch island\*(R" (glue code).  The two target
addresses represent the callee and the \*(L"branch island\*(R".  The
Darwin/PPC linker will prefer the first address and generate a \*(L"bl
callee\*(R" if the \s-1PPC\s0 \*(L"bl\*(R" instruction will reach the callee directly;
otherwise, the linker will generate \*(L"bl L42\*(R" to call the \*(L"branch
island\*(R".  The \*(L"branch island\*(R" is appended to the body of the
calling function; it computes the full 32\-bit address of the callee
and jumps to it.
.Sp
On Mach-O (Darwin) systems, this option directs the compiler emit to
the glue for every direct call, and the Darwin linker decides whether
to use or discard it.
.Sp
In the future, we may cause \s-1GCC\s0 to ignore all longcall specifications
when the linker is known to generate glue.
.IP "\fB\-pthread\fR" 4
.IX Item "-pthread"
Adds support for multithreading with the \fIpthreads\fR library.
This option sets flags for both the preprocessor and linker.
.PP
\fIS/390 and zSeries Options\fR
.IX Subsection "S/390 and zSeries Options"
.PP
These are the \fB\-m\fR options defined for the S/390 and zSeries architecture.
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
.PD 0
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
.PD
Use (do not use) the hardware floating-point instructions and registers
for floating-point operations.  When \fB\-msoft\-float\fR is specified,
functions in \fIlibgcc.a\fR will be used to perform floating-point
operations.  When \fB\-mhard\-float\fR is specified, the compiler
generates \s-1IEEE\s0 floating-point instructions.  This is the default.
.IP "\fB\-mhard\-dfp\fR" 4
.IX Item "-mhard-dfp"
.PD 0
.IP "\fB\-mno\-hard\-dfp\fR" 4
.IX Item "-mno-hard-dfp"
.PD
Use (do not use) the hardware decimal-floating-point instructions for
decimal-floating-point operations.  When \fB\-mno\-hard\-dfp\fR is
specified, functions in \fIlibgcc.a\fR will be used to perform
decimal-floating-point operations.  When \fB\-mhard\-dfp\fR is
specified, the compiler generates decimal-floating-point hardware
instructions.  This is the default for \fB\-march=z9\-ec\fR or higher.
.IP "\fB\-mlong\-double\-64\fR" 4
.IX Item "-mlong-double-64"
.PD 0
.IP "\fB\-mlong\-double\-128\fR" 4
.IX Item "-mlong-double-128"
.PD
These switches control the size of \f(CW\*(C`long double\*(C'\fR type. A size
of 64bit makes the \f(CW\*(C`long double\*(C'\fR type equivalent to the \f(CW\*(C`double\*(C'\fR
type. This is the default.
.IP "\fB\-mbackchain\fR" 4
.IX Item "-mbackchain"
.PD 0
.IP "\fB\-mno\-backchain\fR" 4
.IX Item "-mno-backchain"
.PD
Store (do not store) the address of the caller's frame as backchain pointer
into the callee's stack frame.
A backchain may be needed to allow debugging using tools that do not understand
\&\s-1DWARF\-2\s0 call frame information.
When \fB\-mno\-packed\-stack\fR is in effect, the backchain pointer is stored
at the bottom of the stack frame; when \fB\-mpacked\-stack\fR is in effect,
the backchain is placed into the topmost word of the 96/160 byte register
save area.
.Sp
In general, code compiled with \fB\-mbackchain\fR is call-compatible with
code compiled with \fB\-mmo\-backchain\fR; however, use of the backchain
for debugging purposes usually requires that the whole binary is built with
\&\fB\-mbackchain\fR.  Note that the combination of \fB\-mbackchain\fR,
\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported.  In order
to build a linux kernel use \fB\-msoft\-float\fR.
.Sp
The default is to not maintain the backchain.
.IP "\fB\-mpacked\-stack\fR" 4
.IX Item "-mpacked-stack"
.PD 0
.IP "\fB\-mno\-packed\-stack\fR" 4
.IX Item "-mno-packed-stack"
.PD
Use (do not use) the packed stack layout.  When \fB\-mno\-packed\-stack\fR is
specified, the compiler uses the all fields of the 96/160 byte register save
area only for their default purpose; unused fields still take up stack space.
When \fB\-mpacked\-stack\fR is specified, register save slots are densely
packed at the top of the register save area; unused space is reused for other
purposes, allowing for more efficient use of the available stack space.
However, when \fB\-mbackchain\fR is also in effect, the topmost word of
the save area is always used to store the backchain, and the return address
register is always saved two words below the backchain.
.Sp
As long as the stack frame backchain is not used, code generated with
\&\fB\-mpacked\-stack\fR is call-compatible with code generated with
\&\fB\-mno\-packed\-stack\fR.  Note that some non-FSF releases of \s-1GCC\s0 2.95 for
S/390 or zSeries generated code that uses the stack frame backchain at run
time, not just for debugging purposes.  Such code is not call-compatible
with code compiled with \fB\-mpacked\-stack\fR.  Also, note that the
combination of \fB\-mbackchain\fR,
\&\fB\-mpacked\-stack\fR and \fB\-mhard\-float\fR is not supported.  In order
to build a linux kernel use \fB\-msoft\-float\fR.
.Sp
The default is to not use the packed stack layout.
.IP "\fB\-msmall\-exec\fR" 4
.IX Item "-msmall-exec"
.PD 0
.IP "\fB\-mno\-small\-exec\fR" 4
.IX Item "-mno-small-exec"
.PD
Generate (or do not generate) code using the \f(CW\*(C`bras\*(C'\fR instruction
to do subroutine calls.
This only works reliably if the total executable size does not
exceed 64k.  The default is to use the \f(CW\*(C`basr\*(C'\fR instruction instead,
which does not have this limitation.
.IP "\fB\-m64\fR" 4
.IX Item "-m64"
.PD 0
.IP "\fB\-m31\fR" 4
.IX Item "-m31"
.PD
When \fB\-m31\fR is specified, generate code compliant to the
GNU/Linux for S/390 \s-1ABI\s0.  When \fB\-m64\fR is specified, generate
code compliant to the GNU/Linux for zSeries \s-1ABI\s0.  This allows \s-1GCC\s0 in
particular to generate 64\-bit instructions.  For the \fBs390\fR
targets, the default is \fB\-m31\fR, while the \fBs390x\fR
targets default to \fB\-m64\fR.
.IP "\fB\-mzarch\fR" 4
.IX Item "-mzarch"
.PD 0
.IP "\fB\-mesa\fR" 4
.IX Item "-mesa"
.PD
When \fB\-mzarch\fR is specified, generate code using the
instructions available on z/Architecture.
When \fB\-mesa\fR is specified, generate code using the
instructions available on \s-1ESA/390\s0.  Note that \fB\-mesa\fR is
not possible with \fB\-m64\fR.
When generating code compliant to the GNU/Linux for S/390 \s-1ABI\s0,
the default is \fB\-mesa\fR.  When generating code compliant
to the GNU/Linux for zSeries \s-1ABI\s0, the default is \fB\-mzarch\fR.
.IP "\fB\-mmvcle\fR" 4
.IX Item "-mmvcle"
.PD 0
.IP "\fB\-mno\-mvcle\fR" 4
.IX Item "-mno-mvcle"
.PD
Generate (or do not generate) code using the \f(CW\*(C`mvcle\*(C'\fR instruction
to perform block moves.  When \fB\-mno\-mvcle\fR is specified,
use a \f(CW\*(C`mvc\*(C'\fR loop instead.  This is the default unless optimizing for
size.
.IP "\fB\-mdebug\fR" 4
.IX Item "-mdebug"
.PD 0
.IP "\fB\-mno\-debug\fR" 4
.IX Item "-mno-debug"
.PD
Print (or do not print) additional debug information when compiling.
The default is to not print debug information.
.IP "\fB\-march=\fR\fIcpu-type\fR" 4
.IX Item "-march=cpu-type"
Generate code that will run on \fIcpu-type\fR, which is the name of a system
representing a certain processor type.  Possible values for
\&\fIcpu-type\fR are \fBg5\fR, \fBg6\fR, \fBz900\fR, \fBz990\fR,
\&\fBz9\-109\fR and \fBz9\-ec\fR.
When generating code using the instructions available on z/Architecture,
the default is \fB\-march=z900\fR.  Otherwise, the default is
\&\fB\-march=g5\fR.
.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
.IX Item "-mtune=cpu-type"
Tune to \fIcpu-type\fR everything applicable about the generated code,
except for the \s-1ABI\s0 and the set of available instructions.
The list of \fIcpu-type\fR values is the same as for \fB\-march\fR.
The default is the value used for \fB\-march\fR.
.IP "\fB\-mtpf\-trace\fR" 4
.IX Item "-mtpf-trace"
.PD 0
.IP "\fB\-mno\-tpf\-trace\fR" 4
.IX Item "-mno-tpf-trace"
.PD
Generate code that adds (does not add) in \s-1TPF\s0 \s-1OS\s0 specific branches to trace
routines in the operating system.  This option is off by default, even
when compiling for the \s-1TPF\s0 \s-1OS\s0.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mno\-fused\-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Generate code that uses (does not use) the floating point multiply and
accumulate instructions.  These instructions are generated by default if
hardware floating point is used.
.IP "\fB\-mwarn\-framesize=\fR\fIframesize\fR" 4
.IX Item "-mwarn-framesize=framesize"
Emit a warning if the current function exceeds the given frame size.  Because
this is a compile time check it doesn't need to be a real problem when the program
runs.  It is intended to identify functions which most probably cause
a stack overflow.  It is useful to be used in an environment with limited stack
size e.g. the linux kernel.
.IP "\fB\-mwarn\-dynamicstack\fR" 4
.IX Item "-mwarn-dynamicstack"
Emit a warning if the function calls alloca or uses dynamically
sized arrays.  This is generally a bad idea with a limited stack size.
.IP "\fB\-mstack\-guard=\fR\fIstack-guard\fR" 4
.IX Item "-mstack-guard=stack-guard"
.PD 0
.IP "\fB\-mstack\-size=\fR\fIstack-size\fR" 4
.IX Item "-mstack-size=stack-size"
.PD
If these options are provided the s390 back end emits additional instructions in
the function prologue which trigger a trap if the stack size is \fIstack-guard\fR
bytes above the \fIstack-size\fR (remember that the stack on s390 grows downward).
If the \fIstack-guard\fR option is omitted the smallest power of 2 larger than
the frame size of the compiled function is chosen.
These options are intended to be used to help debugging stack overflow problems.
The additionally emitted code causes only little overhead and hence can also be
used in production like systems without greater performance degradation.  The given
values have to be exact powers of 2 and \fIstack-size\fR has to be greater than
\&\fIstack-guard\fR without exceeding 64k.
In order to be efficient the extra code makes the assumption that the stack starts
at an address aligned to the value given by \fIstack-size\fR.
The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR.
.PP
\fIScore Options\fR
.IX Subsection "Score Options"
.PP
These options are defined for Score implementations:
.IP "\fB\-meb\fR" 4
.IX Item "-meb"
Compile code for big endian mode.  This is the default.
.IP "\fB\-mel\fR" 4
.IX Item "-mel"
Compile code for little endian mode.
.IP "\fB\-mnhwloop\fR" 4
.IX Item "-mnhwloop"
Disable generate bcnz instruction.
.IP "\fB\-muls\fR" 4
.IX Item "-muls"
Enable generate unaligned load and store instruction.
.IP "\fB\-mmac\fR" 4
.IX Item "-mmac"
Enable the use of multiply-accumulate instructions. Disabled by default.
.IP "\fB\-mscore5\fR" 4
.IX Item "-mscore5"
Specify the \s-1SCORE5\s0 as the target architecture.
.IP "\fB\-mscore5u\fR" 4
.IX Item "-mscore5u"
Specify the \s-1SCORE5U\s0 of the target architecture.
.IP "\fB\-mscore7\fR" 4
.IX Item "-mscore7"
Specify the \s-1SCORE7\s0 as the target architecture. This is the default.
.IP "\fB\-mscore7d\fR" 4
.IX Item "-mscore7d"
Specify the \s-1SCORE7D\s0 as the target architecture.
.PP
\fI\s-1SH\s0 Options\fR
.IX Subsection "SH Options"
.PP
These \fB\-m\fR options are defined for the \s-1SH\s0 implementations:
.IP "\fB\-m1\fR" 4
.IX Item "-m1"
Generate code for the \s-1SH1\s0.
.IP "\fB\-m2\fR" 4
.IX Item "-m2"
Generate code for the \s-1SH2\s0.
.IP "\fB\-m2e\fR" 4
.IX Item "-m2e"
Generate code for the SH2e.
.IP "\fB\-m3\fR" 4
.IX Item "-m3"
Generate code for the \s-1SH3\s0.
.IP "\fB\-m3e\fR" 4
.IX Item "-m3e"
Generate code for the SH3e.
.IP "\fB\-m4\-nofpu\fR" 4
.IX Item "-m4-nofpu"
Generate code for the \s-1SH4\s0 without a floating-point unit.
.IP "\fB\-m4\-single\-only\fR" 4
.IX Item "-m4-single-only"
Generate code for the \s-1SH4\s0 with a floating-point unit that only
supports single-precision arithmetic.
.IP "\fB\-m4\-single\fR" 4
.IX Item "-m4-single"
Generate code for the \s-1SH4\s0 assuming the floating-point unit is in
single-precision mode by default.
.IP "\fB\-m4\fR" 4
.IX Item "-m4"
Generate code for the \s-1SH4\s0.
.IP "\fB\-m4a\-nofpu\fR" 4
.IX Item "-m4a-nofpu"
Generate code for the SH4al\-dsp, or for a SH4a in such a way that the
floating-point unit is not used.
.IP "\fB\-m4a\-single\-only\fR" 4
.IX Item "-m4a-single-only"
Generate code for the SH4a, in such a way that no double-precision
floating point operations are used.
.IP "\fB\-m4a\-single\fR" 4
.IX Item "-m4a-single"
Generate code for the SH4a assuming the floating-point unit is in
single-precision mode by default.
.IP "\fB\-m4a\fR" 4
.IX Item "-m4a"
Generate code for the SH4a.
.IP "\fB\-m4al\fR" 4
.IX Item "-m4al"
Same as \fB\-m4a\-nofpu\fR, except that it implicitly passes
\&\fB\-dsp\fR to the assembler.  \s-1GCC\s0 doesn't generate any \s-1DSP\s0
instructions at the moment.
.IP "\fB\-mb\fR" 4
.IX Item "-mb"
Compile code for the processor in big endian mode.
.IP "\fB\-ml\fR" 4
.IX Item "-ml"
Compile code for the processor in little endian mode.
.IP "\fB\-mdalign\fR" 4
.IX Item "-mdalign"
Align doubles at 64\-bit boundaries.  Note that this changes the calling
conventions, and thus some functions from the standard C library will
not work unless you recompile it first with \fB\-mdalign\fR.
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Shorten some address references at link time, when possible; uses the
linker option \fB\-relax\fR.
.IP "\fB\-mbigtable\fR" 4
.IX Item "-mbigtable"
Use 32\-bit offsets in \f(CW\*(C`switch\*(C'\fR tables.  The default is to use
16\-bit offsets.
.IP "\fB\-mfmovd\fR" 4
.IX Item "-mfmovd"
Enable the use of the instruction \f(CW\*(C`fmovd\*(C'\fR.
.IP "\fB\-mhitachi\fR" 4
.IX Item "-mhitachi"
Comply with the calling conventions defined by Renesas.
.IP "\fB\-mrenesas\fR" 4
.IX Item "-mrenesas"
Comply with the calling conventions defined by Renesas.
.IP "\fB\-mno\-renesas\fR" 4
.IX Item "-mno-renesas"
Comply with the calling conventions defined for \s-1GCC\s0 before the Renesas
conventions were available.  This option is the default for all
targets of the \s-1SH\s0 toolchain except for \fBsh-symbianelf\fR.
.IP "\fB\-mnomacsave\fR" 4
.IX Item "-mnomacsave"
Mark the \f(CW\*(C`MAC\*(C'\fR register as call-clobbered, even if
\&\fB\-mhitachi\fR is given.
.IP "\fB\-mieee\fR" 4
.IX Item "-mieee"
Increase IEEE-compliance of floating-point code.
At the moment, this is equivalent to \fB\-fno\-finite\-math\-only\fR.
When generating 16 bit \s-1SH\s0 opcodes, getting IEEE-conforming results for
comparisons of NANs / infinities incurs extra overhead in every
floating point comparison, therefore the default is set to
\&\fB\-ffinite\-math\-only\fR.
.IP "\fB\-minline\-ic_invalidate\fR" 4
.IX Item "-minline-ic_invalidate"
Inline code to invalidate instruction cache entries after setting up
nested function trampolines.
This option has no effect if \-musermode is in effect and the selected
code generation option (e.g. \-m4) does not allow the use of the icbi
instruction.
If the selected code generation option does not allow the use of the icbi
instruction, and \-musermode is not in effect, the inlined code will
manipulate the instruction cache address array directly with an associative
write.  This not only requires privileged mode, but it will also
fail if the cache line had been mapped via the \s-1TLB\s0 and has become unmapped.
.IP "\fB\-misize\fR" 4
.IX Item "-misize"
Dump instruction size and location in the assembly code.
.IP "\fB\-mpadstruct\fR" 4
.IX Item "-mpadstruct"
This option is deprecated.  It pads structures to multiple of 4 bytes,
which is incompatible with the \s-1SH\s0 \s-1ABI\s0.
.IP "\fB\-mspace\fR" 4
.IX Item "-mspace"
Optimize for space instead of speed.  Implied by \fB\-Os\fR.
.IP "\fB\-mprefergot\fR" 4
.IX Item "-mprefergot"
When generating position-independent code, emit function calls using
the Global Offset Table instead of the Procedure Linkage Table.
.IP "\fB\-musermode\fR" 4
.IX Item "-musermode"
Don't generate privileged mode only code; implies \-mno\-inline\-ic_invalidate
if the inlined code would not work in user mode.
This is the default when the target is \f(CW\*(C`sh\-*\-linux*\*(C'\fR.
.IP "\fB\-multcost=\fR\fInumber\fR" 4
.IX Item "-multcost=number"
Set the cost to assume for a multiply insn.
.IP "\fB\-mdiv=\fR\fIstrategy\fR" 4
.IX Item "-mdiv=strategy"
Set the division strategy to use for SHmedia code.  \fIstrategy\fR must be
one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call,
inv:call2, inv:fp .
\&\*(L"fp\*(R" performs the operation in floating point.  This has a very high latency,
but needs only a few instructions, so it might be a good choice if
your code has enough easily exploitable \s-1ILP\s0 to allow the compiler to
schedule the floating point instructions together with other instructions.
Division by zero causes a floating point exception.
\&\*(L"inv\*(R" uses integer operations to calculate the inverse of the divisor,
and then multiplies the dividend with the inverse.  This strategy allows
cse and hoisting of the inverse calculation.  Division by zero calculates
an unspecified result, but does not trap.
\&\*(L"inv:minlat\*(R" is a variant of \*(L"inv\*(R" where if no cse / hoisting opportunities
have been found, or if the entire operation has been hoisted to the same
place, the last stages of the inverse calculation are intertwined with the
final multiply to reduce the overall latency, at the expense of using a few
more instructions, and thus offering fewer scheduling opportunities with
other code.
\&\*(L"call\*(R" calls a library function that usually implements the inv:minlat
strategy.
This gives high code density for m5\-*media\-nofpu compilations.
\&\*(L"call2\*(R" uses a different entry point of the same library function, where it
assumes that a pointer to a lookup table has already been set up, which
exposes the pointer load to cse / code hoisting optimizations.
\&\*(L"inv:call\*(R", \*(L"inv:call2\*(R" and \*(L"inv:fp\*(R" all use the \*(L"inv\*(R" algorithm for initial
code generation, but if the code stays unoptimized, revert to the \*(L"call\*(R",
\&\*(L"call2\*(R", or \*(L"fp\*(R" strategies, respectively.  Note that the
potentially-trapping side effect of division by zero is carried by a
separate instruction, so it is possible that all the integer instructions
are hoisted out, but the marker for the side effect stays where it is.
A recombination to fp operations or a call is not possible in that case.
\&\*(L"inv20u\*(R" and \*(L"inv20l\*(R" are variants of the \*(L"inv:minlat\*(R" strategy.  In the case
that the inverse calculation was nor separated from the multiply, they speed
up division where the dividend fits into 20 bits (plus sign where applicable),
by inserting a test to skip a number of operations in this case; this test
slows down the case of larger dividends.  inv20u assumes the case of a such
a small dividend to be unlikely, and inv20l assumes it to be likely.
.IP "\fB\-mdivsi3_libfunc=\fR\fIname\fR" 4
.IX Item "-mdivsi3_libfunc=name"
Set the name of the library function used for 32 bit signed division to
\&\fIname\fR.  This only affect the name used in the call and inv:call
division strategies, and the compiler will still expect the same
sets of input/output/clobbered registers as if this option was not present.
.IP "\fB\-madjust\-unroll\fR" 4
.IX Item "-madjust-unroll"
Throttle unrolling to avoid thrashing target registers.
This option only has an effect if the gcc code base supports the
\&\s-1TARGET_ADJUST_UNROLL_MAX\s0 target hook.
.IP "\fB\-mindexed\-addressing\fR" 4
.IX Item "-mindexed-addressing"
Enable the use of the indexed addressing mode for SHmedia32/SHcompact.
This is only safe if the hardware and/or \s-1OS\s0 implement 32 bit wrap-around
semantics for the indexed addressing mode.  The architecture allows the
implementation of processors with 64 bit \s-1MMU\s0, which the \s-1OS\s0 could use to
get 32 bit addressing, but since no current hardware implementation supports
this or any other way to make the indexed addressing mode safe to use in
the 32 bit \s-1ABI\s0, the default is \-mno\-indexed\-addressing.
.IP "\fB\-mgettrcost=\fR\fInumber\fR" 4
.IX Item "-mgettrcost=number"
Set the cost assumed for the gettr instruction to \fInumber\fR.
The default is 2 if \fB\-mpt\-fixed\fR is in effect, 100 otherwise.
.IP "\fB\-mpt\-fixed\fR" 4
.IX Item "-mpt-fixed"
Assume pt* instructions won't trap.  This will generally generate better
scheduled code, but is unsafe on current hardware.  The current architecture
definition says that ptabs and ptrel trap when the target anded with 3 is 3.
This has the unintentional effect of making it unsafe to schedule ptabs /
ptrel before a branch, or hoist it out of a loop.  For example,
_\|_do_global_ctors, a part of libgcc that runs constructors at program
startup, calls functions in a list which is delimited by \-1.  With the
\&\-mpt\-fixed option, the ptabs will be done before testing against \-1.
That means that all the constructors will be run a bit quicker, but when
the loop comes to the end of the list, the program crashes because ptabs
loads \-1 into a target register.  Since this option is unsafe for any
hardware implementing the current architecture specification, the default
is \-mno\-pt\-fixed.  Unless the user specifies a specific cost with
\&\fB\-mgettrcost\fR, \-mno\-pt\-fixed also implies \fB\-mgettrcost=100\fR;
this deters register allocation using target registers for storing
ordinary integers.
.IP "\fB\-minvalid\-symbols\fR" 4
.IX Item "-minvalid-symbols"
Assume symbols might be invalid.  Ordinary function symbols generated by
the compiler will always be valid to load with movi/shori/ptabs or
movi/shori/ptrel, but with assembler and/or linker tricks it is possible
to generate symbols that will cause ptabs / ptrel to trap.
This option is only meaningful when \fB\-mno\-pt\-fixed\fR is in effect.
It will then prevent cross-basic-block cse, hoisting and most scheduling
of symbol loads.  The default is \fB\-mno\-invalid\-symbols\fR.
.PP
\fI\s-1SPARC\s0 Options\fR
.IX Subsection "SPARC Options"
.PP
These \fB\-m\fR options are supported on the \s-1SPARC:\s0
.IP "\fB\-mno\-app\-regs\fR" 4
.IX Item "-mno-app-regs"
.PD 0
.IP "\fB\-mapp\-regs\fR" 4
.IX Item "-mapp-regs"
.PD
Specify \fB\-mapp\-regs\fR to generate output using the global registers
2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications.  This
is the default.
.Sp
To be fully \s-1SVR4\s0 \s