ecified size, \f(CW\*(C`byte_loop\*(C'\fR, \f(CW\*(C`loop\*(C'\fR, \f(CW\*(C`unrolled_loop\*(C'\fR for
expanding inline loop, \f(CW\*(C`libcall\*(C'\fR for always expanding library call.
.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
.IX Item "-momit-leaf-frame-pointer"
Don't keep the frame pointer in a register for leaf functions.  This
avoids the instructions to save, set up and restore frame pointers and
makes an extra register available in leaf functions.  The option
\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions
which might make debugging harder.
.IP "\fB\-mtls\-direct\-seg\-refs\fR" 4
.IX Item "-mtls-direct-seg-refs"
.PD 0
.IP "\fB\-mno\-tls\-direct\-seg\-refs\fR" 4
.IX Item "-mno-tls-direct-seg-refs"
.PD
Controls whether \s-1TLS\s0 variables may be accessed with offsets from the
\&\s-1TLS\s0 segment register (\f(CW%gs\fR for 32\-bit, \f(CW%fs\fR for 64\-bit),
or whether the thread base pointer must be added.  Whether or not this
is legal depends on the operating system, and whether it maps the
segment to cover the entire \s-1TLS\s0 area.
.Sp
For systems that use \s-1GNU\s0 libc, the default is on.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mno\-fused\-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Enable automatic generation of fused floating point multiply-add instructions
if the \s-1ISA\s0 supports such instructions.  The \-mfused\-madd option is on by
default.  The fused multiply-add instructions have a different
rounding behavior compared to executing a multiply followed by an add.
.PP
These \fB\-m\fR switches are supported in addition to the above
on \s-1AMD\s0 x86\-64 processors in 64\-bit environments.
.IP "\fB\-m32\fR" 4
.IX Item "-m32"
.PD 0
.IP "\fB\-m64\fR" 4
.IX Item "-m64"
.PD
Generate code for a 32\-bit or 64\-bit environment.
The 32\-bit environment sets int, long and pointer to 32 bits and
generates code that runs on any i386 system.
The 64\-bit environment sets int to 32 bits and long and pointer
to 64 bits and generates code for \s-1AMD\s0's x86\-64 architecture. For
darwin only the \-m64 option turns off the \fB\-fno\-pic\fR and
\&\fB\-mdynamic\-no\-pic\fR options.
.IP "\fB\-mno\-red\-zone\fR" 4
.IX Item "-mno-red-zone"
Do not use a so called red zone for x86\-64 code.  The red zone is mandated
by the x86\-64 \s-1ABI\s0, it is a 128\-byte area beyond the location of the
stack pointer that will not be modified by signal or interrupt handlers
and therefore can be used for temporary data without adjusting the stack
pointer.  The flag \fB\-mno\-red\-zone\fR disables this red zone.
.IP "\fB\-mcmodel=small\fR" 4
.IX Item "-mcmodel=small"
Generate code for the small code model: the program and its symbols must
be linked in the lower 2 \s-1GB\s0 of the address space.  Pointers are 64 bits.
Programs can be statically or dynamically linked.  This is the default
code model.
.IP "\fB\-mcmodel=kernel\fR" 4
.IX Item "-mcmodel=kernel"
Generate code for the kernel code model.  The kernel runs in the
negative 2 \s-1GB\s0 of the address space.
This model has to be used for Linux kernel code.
.IP "\fB\-mcmodel=medium\fR" 4
.IX Item "-mcmodel=medium"
Generate code for the medium model: The program is linked in the lower 2
\&\s-1GB\s0 of the address space but symbols can be located anywhere in the
address space.  Programs can be statically or dynamically linked, but
building of shared libraries are not supported with the medium model.
.IP "\fB\-mcmodel=large\fR" 4
.IX Item "-mcmodel=large"
Generate code for the large model: This model makes no assumptions
about addresses and sizes of sections.
.PP
\fI\s-1IA\-64\s0 Options\fR
.IX Subsection "IA-64 Options"
.PP
These are the \fB\-m\fR options defined for the Intel \s-1IA\-64\s0 architecture.
.IP "\fB\-mbig\-endian\fR" 4
.IX Item "-mbig-endian"
Generate code for a big endian target.  This is the default for HP-UX.
.IP "\fB\-mlittle\-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a little endian target.  This is the default for \s-1AIX5\s0
and GNU/Linux.
.IP "\fB\-mgnu\-as\fR" 4
.IX Item "-mgnu-as"
.PD 0
.IP "\fB\-mno\-gnu\-as\fR" 4
.IX Item "-mno-gnu-as"
.PD
Generate (or don't) code for the \s-1GNU\s0 assembler.  This is the default.
.IP "\fB\-mgnu\-ld\fR" 4
.IX Item "-mgnu-ld"
.PD 0
.IP "\fB\-mno\-gnu\-ld\fR" 4
.IX Item "-mno-gnu-ld"
.PD
Generate (or don't) code for the \s-1GNU\s0 linker.  This is the default.
.IP "\fB\-mno\-pic\fR" 4
.IX Item "-mno-pic"
Generate code that does not use a global pointer register.  The result
is not position independent code, and violates the \s-1IA\-64\s0 \s-1ABI\s0.
.IP "\fB\-mvolatile\-asm\-stop\fR" 4
.IX Item "-mvolatile-asm-stop"
.PD 0
.IP "\fB\-mno\-volatile\-asm\-stop\fR" 4
.IX Item "-mno-volatile-asm-stop"
.PD
Generate (or don't) a stop bit immediately before and after volatile asm
statements.
.IP "\fB\-mregister\-names\fR" 4
.IX Item "-mregister-names"
.PD 0
.IP "\fB\-mno\-register\-names\fR" 4
.IX Item "-mno-register-names"
.PD
Generate (or don't) \fBin\fR, \fBloc\fR, and \fBout\fR register names for
the stacked registers.  This may make assembler output more readable.
.IP "\fB\-mno\-sdata\fR" 4
.IX Item "-mno-sdata"
.PD 0
.IP "\fB\-msdata\fR" 4
.IX Item "-msdata"
.PD
Disable (or enable) optimizations that use the small data section.  This may
be useful for working around optimizer bugs.
.IP "\fB\-mconstant\-gp\fR" 4
.IX Item "-mconstant-gp"
Generate code that uses a single constant global pointer value.  This is
useful when compiling kernel code.
.IP "\fB\-mauto\-pic\fR" 4
.IX Item "-mauto-pic"
Generate code that is self-relocatable.  This implies \fB\-mconstant\-gp\fR.
This is useful when compiling firmware code.
.IP "\fB\-minline\-float\-divide\-min\-latency\fR" 4
.IX Item "-minline-float-divide-min-latency"
Generate code for inline divides of floating point values
using the minimum latency algorithm.
.IP "\fB\-minline\-float\-divide\-max\-throughput\fR" 4
.IX Item "-minline-float-divide-max-throughput"
Generate code for inline divides of floating point values
using the maximum throughput algorithm.
.IP "\fB\-minline\-int\-divide\-min\-latency\fR" 4
.IX Item "-minline-int-divide-min-latency"
Generate code for inline divides of integer values
using the minimum latency algorithm.
.IP "\fB\-minline\-int\-divide\-max\-throughput\fR" 4
.IX Item "-minline-int-divide-max-throughput"
Generate code for inline divides of integer values
using the maximum throughput algorithm.
.IP "\fB\-minline\-sqrt\-min\-latency\fR" 4
.IX Item "-minline-sqrt-min-latency"
Generate code for inline square roots
using the minimum latency algorithm.
.IP "\fB\-minline\-sqrt\-max\-throughput\fR" 4
.IX Item "-minline-sqrt-max-throughput"
Generate code for inline square roots
using the maximum throughput algorithm.
.IP "\fB\-mno\-dwarf2\-asm\fR" 4
.IX Item "-mno-dwarf2-asm"
.PD 0
.IP "\fB\-mdwarf2\-asm\fR" 4
.IX Item "-mdwarf2-asm"
.PD
Don't (or do) generate assembler code for the \s-1DWARF2\s0 line number debugging
info.  This may be useful when not using the \s-1GNU\s0 assembler.
.IP "\fB\-mearly\-stop\-bits\fR" 4
.IX Item "-mearly-stop-bits"
.PD 0
.IP "\fB\-mno\-early\-stop\-bits\fR" 4
.IX Item "-mno-early-stop-bits"
.PD
Allow stop bits to be placed earlier than immediately preceding the
instruction that triggered the stop bit.  This can improve instruction
scheduling, but does not always do so.
.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator can not use.  This is
useful when compiling kernel code.  A register range is specified as
two registers separated by a dash.  Multiple register ranges can be
specified separated by a comma.
.IP "\fB\-mtls\-size=\fR\fItls-size\fR" 4
.IX Item "-mtls-size=tls-size"
Specify bit size of immediate \s-1TLS\s0 offsets.  Valid values are 14, 22, and
64.
.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
.IX Item "-mtune=cpu-type"
Tune the instruction scheduling for a particular \s-1CPU\s0, Valid values are
itanium, itanium1, merced, itanium2, and mckinley.
.IP "\fB\-mt\fR" 4
.IX Item "-mt"
.PD 0
.IP "\fB\-pthread\fR" 4
.IX Item "-pthread"
.PD
Add support for multithreading using the \s-1POSIX\s0 threads library.  This
option sets flags for both the preprocessor and linker.  It does
not affect the thread safety of object code produced by the compiler or
that of libraries supplied with it.  These are HP-UX specific flags.
.IP "\fB\-milp32\fR" 4
.IX Item "-milp32"
.PD 0
.IP "\fB\-mlp64\fR" 4
.IX Item "-mlp64"
.PD
Generate code for a 32\-bit or 64\-bit environment.
The 32\-bit environment sets int, long and pointer to 32 bits.
The 64\-bit environment sets int to 32 bits and long and pointer
to 64 bits.  These are HP-UX specific flags.
.IP "\fB\-mno\-sched\-br\-data\-spec\fR" 4
.IX Item "-mno-sched-br-data-spec"
.PD 0
.IP "\fB\-msched\-br\-data\-spec\fR" 4
.IX Item "-msched-br-data-spec"
.PD
(Dis/En)able data speculative scheduling before reload.
This will result in generation of the ld.a instructions and
the corresponding check instructions (ld.c / chk.a).
The default is 'disable'.
.IP "\fB\-msched\-ar\-data\-spec\fR" 4
.IX Item "-msched-ar-data-spec"
.PD 0
.IP "\fB\-mno\-sched\-ar\-data\-spec\fR" 4
.IX Item "-mno-sched-ar-data-spec"
.PD
(En/Dis)able data speculative scheduling after reload.
This will result in generation of the ld.a instructions and
the corresponding check instructions (ld.c / chk.a).
The default is 'enable'.
.IP "\fB\-mno\-sched\-control\-spec\fR" 4
.IX Item "-mno-sched-control-spec"
.PD 0
.IP "\fB\-msched\-control\-spec\fR" 4
.IX Item "-msched-control-spec"
.PD
(Dis/En)able control speculative scheduling.  This feature is
available only during region scheduling (i.e. before reload).
This will result in generation of the ld.s instructions and
the corresponding check instructions chk.s .
The default is 'disable'.
.IP "\fB\-msched\-br\-in\-data\-spec\fR" 4
.IX Item "-msched-br-in-data-spec"
.PD 0
.IP "\fB\-mno\-sched\-br\-in\-data\-spec\fR" 4
.IX Item "-mno-sched-br-in-data-spec"
.PD
(En/Dis)able speculative scheduling of the instructions that
are dependent on the data speculative loads before reload.
This is effective only with \fB\-msched\-br\-data\-spec\fR enabled.
The default is 'enable'.
.IP "\fB\-msched\-ar\-in\-data\-spec\fR" 4
.IX Item "-msched-ar-in-data-spec"
.PD 0
.IP "\fB\-mno\-sched\-ar\-in\-data\-spec\fR" 4
.IX Item "-mno-sched-ar-in-data-spec"
.PD
(En/Dis)able speculative scheduling of the instructions that
are dependent on the data speculative loads after reload.
This is effective only with \fB\-msched\-ar\-data\-spec\fR enabled.
The default is 'enable'.
.IP "\fB\-msched\-in\-control\-spec\fR" 4
.IX Item "-msched-in-control-spec"
.PD 0
.IP "\fB\-mno\-sched\-in\-control\-spec\fR" 4
.IX Item "-mno-sched-in-control-spec"
.PD
(En/Dis)able speculative scheduling of the instructions that
are dependent on the control speculative loads.
This is effective only with \fB\-msched\-control\-spec\fR enabled.
The default is 'enable'.
.IP "\fB\-msched\-ldc\fR" 4
.IX Item "-msched-ldc"
.PD 0
.IP "\fB\-mno\-sched\-ldc\fR" 4
.IX Item "-mno-sched-ldc"
.PD
(En/Dis)able use of simple data speculation checks ld.c .
If disabled, only chk.a instructions will be emitted to check
data speculative loads.
The default is 'enable'.
.IP "\fB\-mno\-sched\-control\-ldc\fR" 4
.IX Item "-mno-sched-control-ldc"
.PD 0
.IP "\fB\-msched\-control\-ldc\fR" 4
.IX Item "-msched-control-ldc"
.PD
(Dis/En)able use of ld.c instructions to check control speculative loads.
If enabled, in case of control speculative load with no speculatively
scheduled dependent instructions this load will be emitted as ld.sa and
ld.c will be used to check it.
The default is 'disable'.
.IP "\fB\-mno\-sched\-spec\-verbose\fR" 4
.IX Item "-mno-sched-spec-verbose"
.PD 0
.IP "\fB\-msched\-spec\-verbose\fR" 4
.IX Item "-msched-spec-verbose"
.PD
(Dis/En)able printing of the information about speculative motions.
.IP "\fB\-mno\-sched\-prefer\-non\-data\-spec\-insns\fR" 4
.IX Item "-mno-sched-prefer-non-data-spec-insns"
.PD 0
.IP "\fB\-msched\-prefer\-non\-data\-spec\-insns\fR" 4
.IX Item "-msched-prefer-non-data-spec-insns"
.PD
If enabled, data speculative instructions will be chosen for schedule
only if there are no other choices at the moment.  This will make
the use of the data speculation much more conservative.
The default is 'disable'.
.IP "\fB\-mno\-sched\-prefer\-non\-control\-spec\-insns\fR" 4
.IX Item "-mno-sched-prefer-non-control-spec-insns"
.PD 0
.IP "\fB\-msched\-prefer\-non\-control\-spec\-insns\fR" 4
.IX Item "-msched-prefer-non-control-spec-insns"
.PD
If enabled, control speculative instructions will be chosen for schedule
only if there are no other choices at the moment.  This will make
the use of the control speculation much more conservative.
The default is 'disable'.
.IP "\fB\-mno\-sched\-count\-spec\-in\-critical\-path\fR" 4
.IX Item "-mno-sched-count-spec-in-critical-path"
.PD 0
.IP "\fB\-msched\-count\-spec\-in\-critical\-path\fR" 4
.IX Item "-msched-count-spec-in-critical-path"
.PD
If enabled, speculative dependencies will be considered during
computation of the instructions priorities.  This will make the use of the
speculation a bit more conservative.
The default is 'disable'.
.PP
\fIM32C Options\fR
.IX Subsection "M32C Options"
.IP "\fB\-mcpu=\fR\fIname\fR" 4
.IX Item "-mcpu=name"
Select the \s-1CPU\s0 for which code is generated.  \fIname\fR may be one of
\&\fBr8c\fR for the R8C/Tiny series, \fBm16c\fR for the M16C (up to
/60) series, \fBm32cm\fR for the M16C/80 series, or \fBm32c\fR for
the M32C/80 series.
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
Specifies that the program will be run on the simulator.  This causes
an alternate runtime library to be linked in which supports, for
example, file I/O.  You must not use this option when generating
programs that will run on real hardware; you must provide your own
runtime library for whatever I/O functions are needed.
.IP "\fB\-memregs=\fR\fInumber\fR" 4
.IX Item "-memregs=number"
Specifies the number of memory-based pseudo-registers \s-1GCC\s0 will use
during code generation.  These pseudo-registers will be used like real
registers, so there is a tradeoff between \s-1GCC\s0's ability to fit the
code into available registers, and the performance penalty of using
memory instead of registers.  Note that all modules in a program must
be compiled with the same value for this option.  Because of that, you
must not use this option with the default runtime libraries gcc
builds.
.PP
\fIM32R/D Options\fR
.IX Subsection "M32R/D Options"
.PP
These \fB\-m\fR options are defined for Renesas M32R/D architectures:
.IP "\fB\-m32r2\fR" 4
.IX Item "-m32r2"
Generate code for the M32R/2.
.IP "\fB\-m32rx\fR" 4
.IX Item "-m32rx"
Generate code for the M32R/X.
.IP "\fB\-m32r\fR" 4
.IX Item "-m32r"
Generate code for the M32R.  This is the default.
.IP "\fB\-mmodel=small\fR" 4
.IX Item "-mmodel=small"
Assume all objects live in the lower 16MB of memory (so that their addresses
can be loaded with the \f(CW\*(C`ld24\*(C'\fR instruction), and assume all subroutines
are reachable with the \f(CW\*(C`bl\*(C'\fR instruction.
This is the default.
.Sp
The addressability of a particular object can be set with the
\&\f(CW\*(C`model\*(C'\fR attribute.
.IP "\fB\-mmodel=medium\fR" 4
.IX Item "-mmodel=medium"
Assume objects may be anywhere in the 32\-bit address space (the compiler
will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume all subroutines are reachable with the \f(CW\*(C`bl\*(C'\fR instruction.
.IP "\fB\-mmodel=large\fR" 4
.IX Item "-mmodel=large"
Assume objects may be anywhere in the 32\-bit address space (the compiler
will generate \f(CW\*(C`seth/add3\*(C'\fR instructions to load their addresses), and
assume subroutines may not be reachable with the \f(CW\*(C`bl\*(C'\fR instruction
(the compiler will generate the much slower \f(CW\*(C`seth/add3/jl\*(C'\fR
instruction sequence).
.IP "\fB\-msdata=none\fR" 4
.IX Item "-msdata=none"
Disable use of the small data area.  Variables will be put into
one of \fB.data\fR, \fBbss\fR, or \fB.rodata\fR (unless the
\&\f(CW\*(C`section\*(C'\fR attribute has been specified).
This is the default.
.Sp
The small data area consists of sections \fB.sdata\fR and \fB.sbss\fR.
Objects may be explicitly put in the small data area with the
\&\f(CW\*(C`section\*(C'\fR attribute using one of these sections.
.IP "\fB\-msdata=sdata\fR" 4
.IX Item "-msdata=sdata"
Put small global and static data in the small data area, but do not
generate special code to reference them.
.IP "\fB\-msdata=use\fR" 4
.IX Item "-msdata=use"
Put small global and static data in the small data area, and generate
special instructions to reference them.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
Put global and static objects less than or equal to \fInum\fR bytes
into the small data or bss sections instead of the normal data or bss
sections.  The default value of \fInum\fR is 8.
The \fB\-msdata\fR option must be set to one of \fBsdata\fR or \fBuse\fR
for this option to have any effect.
.Sp
All modules should be compiled with the same \fB\-G\fR \fInum\fR value.
Compiling with different values of \fInum\fR may or may not work; if it
doesn't the linker will give an error message\-\-\-incorrect code will not be
generated.
.IP "\fB\-mdebug\fR" 4
.IX Item "-mdebug"
Makes the M32R specific code in the compiler display some statistics
that might help in debugging programs.
.IP "\fB\-malign\-loops\fR" 4
.IX Item "-malign-loops"
Align all loops to a 32\-byte boundary.
.IP "\fB\-mno\-align\-loops\fR" 4
.IX Item "-mno-align-loops"
Do not enforce a 32\-byte alignment for loops.  This is the default.
.IP "\fB\-missue\-rate=\fR\fInumber\fR" 4
.IX Item "-missue-rate=number"
Issue \fInumber\fR instructions per cycle.  \fInumber\fR can only be 1
or 2.
.IP "\fB\-mbranch\-cost=\fR\fInumber\fR" 4
.IX Item "-mbranch-cost=number"
\&\fInumber\fR can only be 1 or 2.  If it is 1 then branches will be
preferred over conditional code, if it is 2, then the opposite will
apply.
.IP "\fB\-mflush\-trap=\fR\fInumber\fR" 4
.IX Item "-mflush-trap=number"
Specifies the trap number to use to flush the cache.  The default is
12.  Valid numbers are between 0 and 15 inclusive.
.IP "\fB\-mno\-flush\-trap\fR" 4
.IX Item "-mno-flush-trap"
Specifies that the cache cannot be flushed by using a trap.
.IP "\fB\-mflush\-func=\fR\fIname\fR" 4
.IX Item "-mflush-func=name"
Specifies the name of the operating system function to call to flush
the cache.  The default is \fI_flush_cache\fR, but a function call
will only be used if a trap is not available.
.IP "\fB\-mno\-flush\-func\fR" 4
.IX Item "-mno-flush-func"
Indicates that there is no \s-1OS\s0 function for flushing the cache.
.PP
\fIM680x0 Options\fR
.IX Subsection "M680x0 Options"
.PP
These are the \fB\-m\fR options defined for M680x0 and ColdFire processors.
The default settings depend on which architecture was selected when
the compiler was configured; the defaults for the most common choices
are given below.
.IP "\fB\-march=\fR\fIarch\fR" 4
.IX Item "-march=arch"
Generate code for a specific M680x0 or ColdFire instruction set
architecture.  Permissible values of \fIarch\fR for M680x0
architectures are: \fB68000\fR, \fB68010\fR, \fB68020\fR,
\&\fB68030\fR, \fB68040\fR, \fB68060\fR and \fBcpu32\fR.  ColdFire
architectures are selected according to Freescale's \s-1ISA\s0 classification
and the permissible values are: \fBisaa\fR, \fBisaaplus\fR,
\&\fBisab\fR and \fBisac\fR.
.Sp
gcc defines a macro \fB_\|_mcf\fR\fIarch\fR\fB_\|_\fR whenever it is generating
code for a ColdFire target.  The \fIarch\fR in this macro is one of the
\&\fB\-march\fR arguments given above.
.Sp
When used together, \fB\-march\fR and \fB\-mtune\fR select code
that runs on a family of similar processors but that is optimized
for a particular microarchitecture.
.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
.IX Item "-mcpu=cpu"
Generate code for a specific M680x0 or ColdFire processor.
The M680x0 \fIcpu\fRs are: \fB68000\fR, \fB68010\fR, \fB68020\fR,
\&\fB68030\fR, \fB68040\fR, \fB68060\fR, \fB68302\fR, \fB68332\fR
and \fBcpu32\fR.  The ColdFire \fIcpu\fRs are given by the table
below, which also classifies the CPUs into families:
.RS 4
.IP "Family : \fB\-mcpu\fR arguments" 4
.IX Item "Family : -mcpu arguments"
.PD 0
.IP "\fB51qe\fR : \fB51qe\fR" 4
.IX Item "51qe : 51qe"
.IP "\fB5206\fR : \fB5202\fR \fB5204\fR \fB5206\fR" 4
.IX Item "5206 : 5202 5204 5206"
.IP "\fB5206e\fR : \fB5206e\fR" 4
.IX Item "5206e : 5206e"
.IP "\fB5208\fR : \fB5207\fR \fB5208\fR" 4
.IX Item "5208 : 5207 5208"
.IP "\fB5211a\fR : \fB5210a\fR \fB5211a\fR" 4
.IX Item "5211a : 5210a 5211a"
.IP "\fB5213\fR : \fB5211\fR \fB5212\fR \fB5213\fR" 4
.IX Item "5213 : 5211 5212 5213"
.IP "\fB5216\fR : \fB5214\fR \fB5216\fR" 4
.IX Item "5216 : 5214 5216"
.IP "\fB52235\fR : \fB52230\fR \fB52231\fR \fB52232\fR \fB52233\fR \fB52234\fR \fB52235\fR" 4
.IX Item "52235 : 52230 52231 52232 52233 52234 52235"
.IP "\fB5225\fR : \fB5224\fR \fB5225\fR" 4
.IX Item "5225 : 5224 5225"
.IP "\fB5235\fR : \fB5232\fR \fB5233\fR \fB5234\fR \fB5235\fR \fB523x\fR" 4
.IX Item "5235 : 5232 5233 5234 5235 523x"
.IP "\fB5249\fR : \fB5249\fR" 4
.IX Item "5249 : 5249"
.IP "\fB5250\fR : \fB5250\fR" 4
.IX Item "5250 : 5250"
.IP "\fB5271\fR : \fB5270\fR \fB5271\fR" 4
.IX Item "5271 : 5270 5271"
.IP "\fB5272\fR : \fB5272\fR" 4
.IX Item "5272 : 5272"
.IP "\fB5275\fR : \fB5274\fR \fB5275\fR" 4
.IX Item "5275 : 5274 5275"
.IP "\fB5282\fR : \fB5280\fR \fB5281\fR \fB5282\fR \fB528x\fR" 4
.IX Item "5282 : 5280 5281 5282 528x"
.IP "\fB5307\fR : \fB5307\fR" 4
.IX Item "5307 : 5307"
.IP "\fB5329\fR : \fB5327\fR \fB5328\fR \fB5329\fR \fB532x\fR" 4
.IX Item "5329 : 5327 5328 5329 532x"
.IP "\fB5373\fR : \fB5372\fR \fB5373\fR \fB537x\fR" 4
.IX Item "5373 : 5372 5373 537x"
.IP "\fB5407\fR : \fB5407\fR" 4
.IX Item "5407 : 5407"
.IP "\fB5475\fR : \fB5470\fR \fB5471\fR \fB5472\fR \fB5473\fR \fB5474\fR \fB5475\fR \fB547x\fR \fB5480\fR \fB5481\fR \fB5482\fR \fB5483\fR \fB5484\fR \fB5485\fR" 4
.IX Item "5475 : 5470 5471 5472 5473 5474 5475 547x 5480 5481 5482 5483 5484 5485"
.RE
.RS 4
.PD
.Sp
\&\fB\-mcpu=\fR\fIcpu\fR overrides \fB\-march=\fR\fIarch\fR if
\&\fIarch\fR is compatible with \fIcpu\fR.  Other combinations of
\&\fB\-mcpu\fR and \fB\-march\fR are rejected.
.Sp
gcc defines the macro \fB_\|_mcf_cpu_\fR\fIcpu\fR when ColdFire target
\&\fIcpu\fR is selected.  It also defines \fB_\|_mcf_family_\fR\fIfamily\fR,
where the value of \fIfamily\fR is given by the table above.
.RE
.IP "\fB\-mtune=\fR\fItune\fR" 4
.IX Item "-mtune=tune"
Tune the code for a particular microarchitecture, within the
constraints set by \fB\-march\fR and \fB\-mcpu\fR.
The M680x0 microarchitectures are: \fB68000\fR, \fB68010\fR,
\&\fB68020\fR, \fB68030\fR, \fB68040\fR, \fB68060\fR
and \fBcpu32\fR.  The ColdFire microarchitectures
are: \fBcfv1\fR, \fBcfv2\fR, \fBcfv3\fR, \fBcfv4\fR and \fBcfv4e\fR.
.Sp
You can also use \fB\-mtune=68020\-40\fR for code that needs
to run relatively well on 68020, 68030 and 68040 targets.
\&\fB\-mtune=68020\-60\fR is similar but includes 68060 targets
as well.  These two options select the same tuning decisions as
\&\fB\-m68020\-40\fR and \fB\-m68020\-60\fR respectively.
.Sp
gcc defines the macros \fB_\|_mc\fR\fIarch\fR and \fB_\|_mc\fR\fIarch\fR\fB_\|_\fR
when tuning for 680x0 architecture \fIarch\fR.  It also defines
\&\fBmc\fR\fIarch\fR unless either \fB\-ansi\fR or a non-GNU \fB\-std\fR
option is used.  If gcc is tuning for a range of architectures,
as selected by \fB\-mtune=68020\-40\fR or \fB\-mtune=68020\-60\fR,
it defines the macros for every architecture in the range.
.Sp
gcc also defines the macro \fB_\|_m\fR\fIuarch\fR\fB_\|_\fR when tuning for
ColdFire microarchitecture \fIuarch\fR, where \fIuarch\fR is one
of the arguments given above.
.IP "\fB\-m68000\fR" 4
.IX Item "-m68000"
.PD 0
.IP "\fB\-mc68000\fR" 4
.IX Item "-mc68000"
.PD
Generate output for a 68000.  This is the default
when the compiler is configured for 68000\-based systems.
It is equivalent to \fB\-march=68000\fR.
.Sp
Use this option for microcontrollers with a 68000 or \s-1EC000\s0 core,
including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
.IP "\fB\-m68010\fR" 4
.IX Item "-m68010"
Generate output for a 68010.  This is the default
when the compiler is configured for 68010\-based systems.
It is equivalent to \fB\-march=68010\fR.
.IP "\fB\-m68020\fR" 4
.IX Item "-m68020"
.PD 0
.IP "\fB\-mc68020\fR" 4
.IX Item "-mc68020"
.PD
Generate output for a 68020.  This is the default
when the compiler is configured for 68020\-based systems.
It is equivalent to \fB\-march=68020\fR.
.IP "\fB\-m68030\fR" 4
.IX Item "-m68030"
Generate output for a 68030.  This is the default when the compiler is
configured for 68030\-based systems.  It is equivalent to
\&\fB\-march=68030\fR.
.IP "\fB\-m68040\fR" 4
.IX Item "-m68040"
Generate output for a 68040.  This is the default when the compiler is
configured for 68040\-based systems.  It is equivalent to
\&\fB\-march=68040\fR.
.Sp
This option inhibits the use of 68881/68882 instructions that have to be
emulated by software on the 68040.  Use this option if your 68040 does not
have code to emulate those instructions.
.IP "\fB\-m68060\fR" 4
.IX Item "-m68060"
Generate output for a 68060.  This is the default when the compiler is
configured for 68060\-based systems.  It is equivalent to
\&\fB\-march=68060\fR.
.Sp
This option inhibits the use of 68020 and 68881/68882 instructions that
have to be emulated by software on the 68060.  Use this option if your 68060
does not have code to emulate those instructions.
.IP "\fB\-mcpu32\fR" 4
.IX Item "-mcpu32"
Generate output for a \s-1CPU32\s0.  This is the default
when the compiler is configured for CPU32\-based systems.
It is equivalent to \fB\-march=cpu32\fR.
.Sp
Use this option for microcontrollers with a
\&\s-1CPU32\s0 or \s-1CPU32+\s0 core, including the 68330, 68331, 68332, 68333, 68334,
68336, 68340, 68341, 68349 and 68360.
.IP "\fB\-m5200\fR" 4
.IX Item "-m5200"
Generate output for a 520X ColdFire \s-1CPU\s0.  This is the default
when the compiler is configured for 520X\-based systems.
It is equivalent to \fB\-mcpu=5206\fR, and is now deprecated
in favor of that option.
.Sp
Use this option for microcontroller with a 5200 core, including
the \s-1MCF5202\s0, \s-1MCF5203\s0, \s-1MCF5204\s0 and \s-1MCF5206\s0.
.IP "\fB\-m5206e\fR" 4
.IX Item "-m5206e"
Generate output for a 5206e ColdFire \s-1CPU\s0.  The option is now
deprecated in favor of the equivalent \fB\-mcpu=5206e\fR.
.IP "\fB\-m528x\fR" 4
.IX Item "-m528x"
Generate output for a member of the ColdFire 528X family.
The option is now deprecated in favor of the equivalent
\&\fB\-mcpu=528x\fR.
.IP "\fB\-m5307\fR" 4
.IX Item "-m5307"
Generate output for a ColdFire 5307 \s-1CPU\s0.  The option is now deprecated
in favor of the equivalent \fB\-mcpu=5307\fR.
.IP "\fB\-m5407\fR" 4
.IX Item "-m5407"
Generate output for a ColdFire 5407 \s-1CPU\s0.  The option is now deprecated
in favor of the equivalent \fB\-mcpu=5407\fR.
.IP "\fB\-mcfv4e\fR" 4
.IX Item "-mcfv4e"
Generate output for a ColdFire V4e family \s-1CPU\s0 (e.g. 547x/548x).
This includes use of hardware floating point instructions.
The option is equivalent to \fB\-mcpu=547x\fR, and is now
deprecated in favor of that option.
.IP "\fB\-m68020\-40\fR" 4
.IX Item "-m68020-40"
Generate output for a 68040, without using any of the new instructions.
This results in code which can run relatively efficiently on either a
68020/68881 or a 68030 or a 68040.  The generated code does use the
68881 instructions that are emulated on the 68040.
.Sp
The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-40\fR.
.IP "\fB\-m68020\-60\fR" 4
.IX Item "-m68020-60"
Generate output for a 68060, without using any of the new instructions.
This results in code which can run relatively efficiently on either a
68020/68881 or a 68030 or a 68040.  The generated code does use the
68881 instructions that are emulated on the 68060.
.Sp
The option is equivalent to \fB\-march=68020\fR \fB\-mtune=68020\-60\fR.
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
.PD 0
.IP "\fB\-m68881\fR" 4
.IX Item "-m68881"
.PD
Generate floating-point instructions.  This is the default for 68020
and above, and for ColdFire devices that have an \s-1FPU\s0.  It defines the
macro \fB_\|_HAVE_68881_\|_\fR on M680x0 targets and \fB_\|_mcffpu_\|_\fR
on ColdFire targets.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Do not generate floating-point instructions; use library calls instead.
This is the default for 68000, 68010, and 68832 targets.  It is also
the default for ColdFire devices that have no \s-1FPU\s0.
.IP "\fB\-mdiv\fR" 4
.IX Item "-mdiv"
.PD 0
.IP "\fB\-mno\-div\fR" 4
.IX Item "-mno-div"
.PD
Generate (do not generate) ColdFire hardware divide and remainder
instructions.  If \fB\-march\fR is used without \fB\-mcpu\fR,
the default is \*(L"on\*(R" for ColdFire architectures and \*(L"off\*(R" for M680x0
architectures.  Otherwise, the default is taken from the target \s-1CPU\s0
(either the default \s-1CPU\s0, or the one specified by \fB\-mcpu\fR).  For
example, the default is \*(L"off\*(R" for \fB\-mcpu=5206\fR and \*(L"on\*(R" for
\&\fB\-mcpu=5206e\fR.
.Sp
gcc defines the macro \fB_\|_mcfhwdiv_\|_\fR when this option is enabled.
.IP "\fB\-mshort\fR" 4
.IX Item "-mshort"
Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
Additionally, parameters passed on the stack are also aligned to a
16\-bit boundary even on targets whose \s-1API\s0 mandates promotion to 32\-bit.
.IP "\fB\-mno\-short\fR" 4
.IX Item "-mno-short"
Do not consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide.  This is the default.
.IP "\fB\-mnobitfield\fR" 4
.IX Item "-mnobitfield"
.PD 0
.IP "\fB\-mno\-bitfield\fR" 4
.IX Item "-mno-bitfield"
.PD
Do not use the bit-field instructions.  The \fB\-m68000\fR, \fB\-mcpu32\fR
and \fB\-m5200\fR options imply \fB\-mnobitfield\fR.
.IP "\fB\-mbitfield\fR" 4
.IX Item "-mbitfield"
Do use the bit-field instructions.  The \fB\-m68020\fR option implies
\&\fB\-mbitfield\fR.  This is the default if you use a configuration
designed for a 68020.
.IP "\fB\-mrtd\fR" 4
.IX Item "-mrtd"
Use a different function-calling convention, in which functions
that take a fixed number of arguments return with the \f(CW\*(C`rtd\*(C'\fR
instruction, which pops their arguments while returning.  This
saves one instruction in the caller since there is no need to pop
the arguments there.
.Sp
This calling convention is incompatible with the one normally
used on Unix, so you cannot use it if you need to call libraries
compiled with the Unix compiler.
.Sp
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
otherwise incorrect code will be generated for calls to those
functions.
.Sp
In addition, seriously incorrect code will result if you call a
function with too many arguments.  (Normally, extra arguments are
harmlessly ignored.)
.Sp
The \f(CW\*(C`rtd\*(C'\fR instruction is supported by the 68010, 68020, 68030,
68040, 68060 and \s-1CPU32\s0 processors, but not by the 68000 or 5200.
.IP "\fB\-mno\-rtd\fR" 4
.IX Item "-mno-rtd"
Do not use the calling conventions selected by \fB\-mrtd\fR.
This is the default.
.IP "\fB\-malign\-int\fR" 4
.IX Item "-malign-int"
.PD 0
.IP "\fB\-mno\-align\-int\fR" 4
.IX Item "-mno-align-int"
.PD
Control whether \s-1GCC\s0 aligns \f(CW\*(C`int\*(C'\fR, \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`long long\*(C'\fR,
\&\f(CW\*(C`float\*(C'\fR, \f(CW\*(C`double\*(C'\fR, and \f(CW\*(C`long double\*(C'\fR variables on a 32\-bit
boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR).
Aligning variables on 32\-bit boundaries produces code that runs somewhat
faster on processors with 32\-bit busses at the expense of more memory.
.Sp
\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will
align structures containing the above types  differently than
most published application binary interface specifications for the m68k.
.IP "\fB\-mpcrel\fR" 4
.IX Item "-mpcrel"
Use the pc-relative addressing mode of the 68000 directly, instead of
using a global offset table.  At present, this option implies \fB\-fpic\fR,
allowing at most a 16\-bit offset for pc-relative addressing.  \fB\-fPIC\fR is
not presently supported with \fB\-mpcrel\fR, though this could be supported for
68020 and higher processors.
.IP "\fB\-mno\-strict\-align\fR" 4
.IX Item "-mno-strict-align"
.PD 0
.IP "\fB\-mstrict\-align\fR" 4
.IX Item "-mstrict-align"
.PD
Do not (do) assume that unaligned memory references will be handled by
the system.
.IP "\fB\-msep\-data\fR" 4
.IX Item "-msep-data"
Generate code that allows the data segment to be located in a different
area of memory from the text segment.  This allows for execute in place in
an environment without virtual memory management.  This option implies
\&\fB\-fPIC\fR.
.IP "\fB\-mno\-sep\-data\fR" 4
.IX Item "-mno-sep-data"
Generate code that assumes that the data segment follows the text segment.
This is the default.
.IP "\fB\-mid\-shared\-library\fR" 4
.IX Item "-mid-shared-library"
Generate code that supports shared libraries via the library \s-1ID\s0 method.
This allows for execute in place and shared libraries in an environment
without virtual memory management.  This option implies \fB\-fPIC\fR.
.IP "\fB\-mno\-id\-shared\-library\fR" 4
.IX Item "-mno-id-shared-library"
Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
This is the default.
.IP "\fB\-mshared\-library\-id=n\fR" 4
.IX Item "-mshared-library-id=n"
Specified the identification number of the \s-1ID\s0 based shared library being
compiled.  Specifying a value of 0 will generate more compact code, specifying
other values will force the allocation of that number to the current
library but is no more space or time efficient than omitting this option.
.PP
\fIM68hc1x Options\fR
.IX Subsection "M68hc1x Options"
.PP
These are the \fB\-m\fR options defined for the 68hc11 and 68hc12
microcontrollers.  The default values for these options depends on
which style of microcontroller was selected when the compiler was configured;
the defaults for the most common choices are given below.
.IP "\fB\-m6811\fR" 4
.IX Item "-m6811"
.PD 0
.IP "\fB\-m68hc11\fR" 4
.IX Item "-m68hc11"
.PD
Generate output for a 68HC11.  This is the default
when the compiler is configured for 68HC11\-based systems.
.IP "\fB\-m6812\fR" 4
.IX Item "-m6812"
.PD 0
.IP "\fB\-m68hc12\fR" 4
.IX Item "-m68hc12"
.PD
Generate output for a 68HC12.  This is the default
when the compiler is configured for 68HC12\-based systems.
.IP "\fB\-m68S12\fR" 4
.IX Item "-m68S12"
.PD 0
.IP "\fB\-m68hcs12\fR" 4
.IX Item "-m68hcs12"
.PD
Generate output for a 68HCS12.
.IP "\fB\-mauto\-incdec\fR" 4
.IX Item "-mauto-incdec"
Enable the use of 68HC12 pre and post auto-increment and auto-decrement
addressing modes.
.IP "\fB\-minmax\fR" 4
.IX Item "-minmax"
.PD 0
.IP "\fB\-nominmax\fR" 4
.IX Item "-nominmax"
.PD
Enable the use of 68HC12 min and max instructions.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.IP "\fB\-mno\-long\-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Treat all calls as being far away (near).  If calls are assumed to be
far away, the compiler will use the \f(CW\*(C`call\*(C'\fR instruction to
call a function and the \f(CW\*(C`rtc\*(C'\fR instruction for returning.
.IP "\fB\-mshort\fR" 4
.IX Item "-mshort"
Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
.IP "\fB\-msoft\-reg\-count=\fR\fIcount\fR" 4
.IX Item "-msoft-reg-count=count"
Specify the number of pseudo-soft registers which are used for the
code generation.  The maximum number is 32.  Using more pseudo-soft
register may or may not result in better code depending on the program.
The default is 4 for 68HC11 and 2 for 68HC12.
.PP
\fIMCore Options\fR
.IX Subsection "MCore Options"
.PP
These are the \fB\-m\fR options defined for the Motorola M*Core
processors.
.IP "\fB\-mhardlit\fR" 4
.IX Item "-mhardlit"
.PD 0
.IP "\fB\-mno\-hardlit\fR" 4
.IX Item "-mno-hardlit"
.PD
Inline constants into the code stream if it can be done in two
instructions or less.
.IP "\fB\-mdiv\fR" 4
.IX Item "-mdiv"
.PD 0
.IP "\fB\-mno\-div\fR" 4
.IX Item "-mno-div"
.PD
Use the divide instruction.  (Enabled by default).
.IP "\fB\-mrelax\-immediate\fR" 4
.IX Item "-mrelax-immediate"
.PD 0
.IP "\fB\-mno\-relax\-immediate\fR" 4
.IX Item "-mno-relax-immediate"
.PD
Allow arbitrary sized immediates in bit operations.
.IP "\fB\-mwide\-bitfields\fR" 4
.IX Item "-mwide-bitfields"
.PD 0
.IP "\fB\-mno\-wide\-bitfields\fR" 4
.IX Item "-mno-wide-bitfields"
.PD
Always treat bit-fields as int-sized.
.IP "\fB\-m4byte\-functions\fR" 4
.IX Item "-m4byte-functions"
.PD 0
.IP "\fB\-mno\-4byte\-functions\fR" 4
.IX Item "-mno-4byte-functions"
.PD
Force all functions to be aligned to a four byte boundary.
.IP "\fB\-mcallgraph\-data\fR" 4
.IX Item "-mcallgraph-data"
.PD 0
.IP "\fB\-mno\-callgraph\-data\fR" 4
.IX Item "-mno-callgraph-data"
.PD
Emit callgraph information.
.IP "\fB\-mslow\-bytes\fR" 4
.IX Item "-mslow-bytes"
.PD 0
.IP "\fB\-mno\-slow\-bytes\fR" 4
.IX Item "-mno-slow-bytes"
.PD
Prefer word access when reading byte quantities.
.IP "\fB\-mlittle\-endian\fR" 4
.IX Item "-mlittle-endian"
.PD 0
.IP "\fB\-mbig\-endian\fR" 4
.IX Item "-mbig-endian"
.PD
Generate code for a little endian target.
.IP "\fB\-m210\fR" 4
.IX Item "-m210"
.PD 0
.IP "\fB\-m340\fR" 4
.IX Item "-m340"
.PD
Generate code for the 210 processor.
.PP
\fI\s-1MIPS\s0 Options\fR
.IX Subsection "MIPS Options"
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Generate big-endian code.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Generate little-endian code.  This is the default for \fBmips*el\-*\-*\fR
configurations.
.IP "\fB\-march=\fR\fIarch\fR" 4
.IX Item "-march=arch"
Generate code that will run on \fIarch\fR, which can be the name of a
generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor.
The \s-1ISA\s0 names are:
\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR,
\&\fBmips32\fR, \fBmips32r2\fR, and \fBmips64\fR.
The processor names are:
\&\fB4kc\fR, \fB4km\fR, \fB4kp\fR, \fB4ksc\fR,
\&\fB4kec\fR, \fB4kem\fR, \fB4kep\fR, \fB4ksd\fR,
\&\fB5kc\fR, \fB5kf\fR,
\&\fB20kc\fR,
\&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR,
\&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR,
\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR,
\&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR,
\&\fBm4k\fR,
\&\fBorion\fR,
\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR,
\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR,
\&\fBrm7000\fR, \fBrm9000\fR,
\&\fBsb1\fR,
\&\fBsr71000\fR,
\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR,
\&\fBvr5000\fR, \fBvr5400\fR and \fBvr5500\fR.
The special value \fBfrom-abi\fR selects the
most compatible architecture for the selected \s-1ABI\s0 (that is,
\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs).
.Sp
In processor names, a final \fB000\fR can be abbreviated as \fBk\fR
(for example, \fB\-march=r2k\fR).  Prefixes are optional, and
\&\fBvr\fR may be written \fBr\fR.
.Sp
Names of the form \fIn\fR\fBf2_1\fR refer to processors with
FPUs clocked at half the rate of the core, names of the form
\&\fIn\fR\fBf1_1\fR refer to processors with FPUs clocked at the same
rate as the core, and names of the form \fIn\fR\fBf3_2\fR refer to
processors with FPUs clocked a ratio of 3:2 with respect to the core.
For compatibility reasons, \fIn\fR\fBf\fR is accepted as a synonym
for \fIn\fR\fBf2_1\fR while \fIn\fR\fBx\fR and \fIb\fR\fBfx\fR are
accepted as synonyms for \fIn\fR\fBf1_1\fR.
.Sp
\&\s-1GCC\s0 defines two macros based on the value of this option.  The first
is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as
a string.  The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR,
where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR.
For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR
to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR.
.Sp
Note that the \fB_MIPS_ARCH\fR macro uses the processor names given
above.  In other words, it will have the full prefix and will not
abbreviate \fB000\fR as \fBk\fR.  In the case of \fBfrom-abi\fR,
the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or
\&\fB\*(L"mips3\*(R"\fR).  It names the default architecture when no
\&\fB\-march\fR option is given.
.IP "\fB\-mtune=\fR\fIarch\fR" 4
.IX Item "-mtune=arch"
Optimize for \fIarch\fR.  Among other things, this option controls
the way instructions are scheduled, and the perceived cost of arithmetic
operations.  The list of \fIarch\fR values is the same as for
\&\fB\-march\fR.
.Sp
When this option is not used, \s-1GCC\s0 will optimize for the processor
specified by \fB\-march\fR.  By using \fB\-march\fR and
\&\fB\-mtune\fR together, it is possible to generate code that will
run on a family of processors, but optimize the code for one
particular member of that family.
.Sp
\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and
\&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the
\&\fB\-march\fR ones described above.
.IP "\fB\-mips1\fR" 4
.IX Item "-mips1"
Equivalent to \fB\-march=mips1\fR.
.IP "\fB\-mips2\fR" 4
.IX Item "-mips2"
Equivalent to \fB\-march=mips2\fR.
.IP "\fB\-mips3\fR" 4
.IX Item "-mips3"
Equivalent to \fB\-march=mips3\fR.
.IP "\fB\-mips4\fR" 4
.IX Item "-mips4"
Equivalent to \fB\-march=mips4\fR.
.IP "\fB\-mips32\fR" 4
.IX Item "-mips32"
Equivalent to \fB\-march=mips32\fR.
.IP "\fB\-mips32r2\fR" 4
.IX Item "-mips32r2"
Equivalent to \fB\-march=mips32r2\fR.
.IP "\fB\-mips64\fR" 4
.IX Item "-mips64"
Equivalent to \fB\-march=mips64\fR.
.IP "\fB\-mips16\fR" 4
.IX Item "-mips16"
.PD 0
.IP "\fB\-mno\-mips16\fR" 4
.IX Item "-mno-mips16"
.PD
Generate (do not generate) \s-1MIPS16\s0 code.  If \s-1GCC\s0 is targetting a
\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it will make use of the MIPS16e \s-1ASE\s0.
.Sp
\&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis
by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes.
.IP "\fB\-mflip\-mips16\fR" 4
.IX Item "-mflip-mips16"
Generate \s-1MIPS16\s0 code on alternating functions.  This option is provided
for regression testing of mixed MIPS16/non\-MIPS16 code generation, and is
not intended for ordinary use in compiling user code.
.IP "\fB\-minterlink\-mips16\fR" 4
.IX Item "-minterlink-mips16"
.PD 0
.IP "\fB\-mno\-interlink\-mips16\fR" 4
.IX Item "-mno-interlink-mips16"
.PD
Require (do not require) that non\-MIPS16 code be link-compatible with
\&\s-1MIPS16\s0 code.
.Sp
For example, non\-MIPS16 code cannot jump directly to \s-1MIPS16\s0 code;
it must either use a call or an indirect jump.  \fB\-minterlink\-mips16\fR
therefore disables direct jumps unless \s-1GCC\s0 knows that the target of the
jump is not \s-1MIPS16\s0.
.IP "\fB\-mabi=32\fR" 4
.IX Item "-mabi=32"
.PD 0
.IP "\fB\-mabi=o64\fR" 4
.IX Item "-mabi=o64"
.IP "\fB\-mabi=n32\fR" 4
.IX Item "-mabi=n32"
.IP "\fB\-mabi=64\fR" 4
.IX Item "-mabi=64"
.IP "\fB\-mabi=eabi\fR" 4
.IX Item "-mabi=eabi"
.PD
Generate code for the given \s-1ABI\s0.
.Sp
Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant.  \s-1GCC\s0 normally
generates 64\-bit code when you select a 64\-bit architecture, but you
can use \fB\-mgp32\fR to get 32\-bit code instead.
.Sp
For information about the O64 \s-1ABI\s0, see
<\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>.
.Sp
\&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers
are 64 rather than 32 bits wide.  You can select this combination with
\&\fB\-mabi=32\fR \fB\-mfp64\fR.  This \s-1ABI\s0 relies on the \fBmthc1\fR
and \fBmfhc1\fR instructions and is therefore only supported for
\&\s-1MIPS32R2\s0 processors.
.Sp
The register assignments for arguments and return values remain the
same, but each scalar value is passed in a single 64\-bit register
rather than a pair of 32\-bit registers.  For example, scalar
floating-point values are returned in \fB\f(CB$f0\fB\fR only, not a
\&\fB\f(CB$f0\fB\fR/\fB\f(CB$f1\fB\fR pair.  The set of call-saved registers also
remains the same, but all 64 bits are saved.
.IP "\fB\-mabicalls\fR" 4
.IX Item "-mabicalls"
.PD 0
.IP "\fB\-mno\-abicalls\fR" 4
.IX Item "-mno-abicalls"
.PD
Generate (do not generate) code that is suitable for SVR4\-style
dynamic objects.  \fB\-mabicalls\fR is the default for SVR4\-based
systems.
.IP "\fB\-mshared\fR" 4
.IX Item "-mshared"
.PD 0
.IP "\fB\-mno\-shared\fR" 4
.IX Item "-mno-shared"
.PD
Generate (do not generate) code that is fully position-independent,
and that can therefore be linked into shared libraries.  This option
only affects \fB\-mabicalls\fR.
.Sp
All \fB\-mabicalls\fR code has traditionally been position-independent,
regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR.  However,
as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute
accesses for locally-binding symbols.  It can also use shorter \s-1GP\s0
initialization sequences and generate direct calls to locally-defined
functions.  This mode is selected by \fB\-mno\-shared\fR.
.Sp
\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates
objects that can only be linked by the \s-1GNU\s0 linker.  However, the option
does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0
of relocatable objects.  Using \fB\-mno\-shared\fR will generally make
executables both smaller and quicker.
.Sp
\&\fB\-mshared\fR is the default.
.IP "\fB\-mxgot\fR" 4
.IX Item "-mxgot"
.PD 0
.IP "\fB\-mno\-xgot\fR" 4
.IX Item "-mno-xgot"
.PD
Lift (do not lift) the usual restrictions on the size of the global
offset table.
.Sp
\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0.
While this is relatively efficient, it will only work if the \s-1GOT\s0
is smaller than about 64k.  Anything larger will cause the linker
to report an error such as:
.Sp
.Vb 1
\&        relocation truncated to fit: R_MIPS_GOT16 foobar
.Ve
.Sp
If this happens, you should recompile your code with \fB\-mxgot\fR.
It should then work with very large GOTs, although it will also be
less efficient, since it will take three instructions to fetch the
value of a global symbol.
.Sp
Note that some linkers can create multiple GOTs.  If you have such a
linker, you should only need to use \fB\-mxgot\fR when a single object
file accesses more than 64k's worth of \s-1GOT\s0 entries.  Very few do.
.Sp
These options have no effect unless \s-1GCC\s0 is generating position
independent code.
.IP "\fB\-mgp32\fR" 4
.IX Item "-mgp32"
Assume that general-purpose registers are 32 bits wide.
.IP "\fB\-mgp64\fR" 4
.IX Item "-mgp64"
Assume that general-purpose registers are 64 bits wide.
.IP "\fB\-mfp32\fR" 4
.IX Item "-mfp32"
Assume that floating-point registers are 32 bits wide.
.IP "\fB\-mfp64\fR" 4
.IX Item "-mfp64"
Assume that floating-point registers are 64 bits wide.
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
Use floating-point coprocessor instructions.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Do not use floating-point coprocessor instructions.  Implement
floating-point calculations using library calls instead.
.IP "\fB\-msingle\-float\fR" 4
.IX Item "-msingle-float"
Assume that the floating-point coprocessor only supports single-precision
operations.
.IP "\fB\-mdouble\-float\fR" 4
.IX Item "-mdouble-float"
Assume that the floating-point coprocessor supports double-precision
operations.  This is the default.
.IP "\fB\-mllsc\fR" 4
.IX Item "-mllsc"
.PD 0
.IP "\fB\-mno\-llsc\fR" 4
.IX Item "-mno-llsc"
.PD
Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to
implement atomic memory built-in functions.  When neither option is
specified, \s-1GCC\s0 will use the instructions if the target architecture
supports them.
.Sp
\&\fB\-mllsc\fR is useful if the runtime environment can emulate the
instructions and \fB\-mno\-llsc\fR can be useful when compiling for
nonstandard ISAs.  You can make either option the default by
configuring \s-1GCC\s0 with \fB\-\-with\-llsc\fR and \fB\-\-without\-llsc\fR
respectively.  \fB\-\-with\-llsc\fR is the default for some
configurations; see the installation documentation for details.
.IP "\fB\-mdsp\fR" 4
.IX Item "-mdsp"
.PD 0
.IP "\fB\-mno\-dsp\fR" 4
.IX Item "-mno-dsp"
.PD
Use (do not use) revision 1 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0.
  This option defines the
preprocessor macro \fB_\|_mips_dsp\fR.  It also defines
\&\fB_\|_mips_dsp_rev\fR to 1.
.IP "\fB\-mdspr2\fR" 4
.IX Item "-mdspr2"
.PD 0
.IP "\fB\-mno\-dspr2\fR" 4
.IX Item "-mno-dspr2"
.PD
Use (do not use) revision 2 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0.
  This option defines the
preprocessor macros \fB_\|_mips_dsp\fR and \fB_\|_mips_dspr2\fR.
It also defines \fB_\|_mips_dsp_rev\fR to 2.
.IP "\fB\-msmartmips\fR" 4
.IX Item "-msmartmips"
.PD 0
.IP "\fB\-mno\-smartmips\fR" 4
.IX Item "-mno-smartmips"
.PD
Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE\s0.
.IP "\fB\-mpaired\-single\fR" 4
.IX Item "-mpaired-single"
.PD 0
.IP "\fB\-mno\-paired\-single\fR" 4
.IX Item "-mno-paired-single"
.PD
Use (do not use) paired-single floating-point instructions.
  This option requires
hardware floating-point support to be enabled.
.IP "\fB\-mdmx\fR" 4
.IX Item "-mdmx"
.PD 0
.IP "\fB\-mno\-mdmx\fR" 4
.IX Item "-mno-mdmx"
.PD
Use (do not use) \s-1MIPS\s0 Digital Media Extension instructions.
This option can only be used when generating 64\-bit code and requires
hardware floating-point support to be enabled.
.IP "\fB\-mips3d\fR" 4
.IX Item "-mips3d"
.PD 0
.IP "\fB\-mno\-mips3d\fR" 4
.IX Item "-mno-mips3d"
.PD
Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0.  
The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR.
.IP "\fB\-mmt\fR" 4
.IX Item "-mmt"
.PD 0
.IP "\fB\-mno\-mt\fR" 4
.IX Item "-mno-mt"
.PD
Use (do not use) \s-1MT\s0 Multithreading instructions.
.IP "\fB\-mlong64\fR" 4
.IX Item "-mlong64"
Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide.  See \fB\-mlong32\fR for
an explanation of the default and the way that the pointer size is
determined.
.IP "\fB\-mlong32\fR" 4
.IX Item "-mlong32"
Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide.
.Sp
The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on
the \s-1ABI\s0.  All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs.  The n64 \s-1ABI\s0
uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use
32\-bit \f(CW\*(C`long\*(C'\fRs.  Pointers are the same size as \f(CW\*(C`long\*(C'\fRs,
or the same size as integer registers, whichever is smaller.
.IP "\fB\-msym32\fR" 4
.IX Item "-msym32"
.PD 0
.IP "\fB\-mno\-sym32\fR" 4
.IX Item "-mno-sym32"
.PD
Assume (do not assume) that all symbols have 32\-bit values, regardless
of the selected \s-1ABI\s0.  This option is useful in combination with
\&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0
to generate shorter and faster references to symbolic addresses.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
Put definitions of externally-visible data in a small data section
if that data is no bigger than \fInum\fR bytes.  \s-1GCC\s0 can then access
the data more efficiently; see \fB\-mgpopt\fR for details.
.Sp
The default \fB\-G\fR option depends on the configuration.
.IP "\fB\-mlocal\-sdata\fR" 4
.IX Item "-mlocal-sdata"
.PD 0
.IP "\fB\-mno\-local\-sdata\fR" 4
.IX Item "-mno-local-sdata"
.PD
Extend (do not extend) the \fB\-G\fR behavior to local data too,
such as to static variables in C.  \fB\-mlocal\-sdata\fR is the
default for all configurations.
.Sp
If the linker complains that an application is using too much small data,
you might want to try rebuilding the less performance-critical parts with
\&\fB\-mno\-local\-sdata\fR.  You might also want to build large
libraries with \fB\-mno\-local\-sdata\fR, so that the libraries leave
more room for the main program.
.IP "\fB\-mextern\-sdata\fR" 4
.IX Item "-mextern-sdata"
.PD 0
.IP "\fB\-mno\-extern\-sdata\fR" 4
.IX Item "-mno-extern-sdata"
.PD
Assume (do not assume) that externally-defined data will be in
a small data section if that data is within the \fB\-G\fR limit.
\&\fB\-mextern\-sdata\fR is the default for all configurations.
.Sp
If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR
\&\fInum\fR \fB\-mgpopt\fR, and \fIMod\fR references a variable \fIVar\fR
that is no bigger than \fInum\fR bytes, you must make sure that \fIVar\fR
is placed in a small data section.  If \fIVar\fR is defined by another
module, you must either compile that module with a high-enough
\&\fB\-G\fR setting or attach a \f(CW\*(C`section\*(C'\fR attribute to \fIVar\fR's
definition.  If \fIVar\fR is common, you must link the application
with a high-enough \fB\-G\fR setting.
.Sp
The easiest way of satisfying these restrictions is to compile
and link every module with the same \fB\-G\fR option.  However,
you may wish to build a library that supports several different
small data limits.  You can do this by compiling the library with
the highest supported \fB\-G\fR setting and additionally using
\&\fB\-mno\-extern\-sdata\fR to stop the library from making assumptions
about externally-defined data.
.IP "\fB\-mgpopt\fR" 4
.IX Item "-mgpopt"
.PD 0
.IP "\fB\-mno\-gpopt\fR" 4
.IX Item "-mno-gpopt"
.PD
Use (do not use) GP-relative accesses for symbols that are known to be
in a small data section; see \fB\-G\fR, \fB\-mlocal\-sdata\fR and
\&\fB\-mextern\-sdata\fR.  \fB\-mgpopt\fR is the default for all
configurations.
.Sp
\&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register
might not hold the value of \f(CW\*(C`_gp\*(C'\fR.  For example, if the code is
part of a library that might be used in a boot monitor, programs that
call boot monitor routines will pass an unknown value in \f(CW$gp\fR.
(In such situations, the boot monitor itself would usually be compiled
with \fB\-G0\fR.)
.Sp
\&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and
\&\fB\-mno\-extern\-sdata\fR.
.IP "\fB\-membedded\-data\fR" 4
.IX Item "-membedded-data"
.PD 0
.IP "\fB\-mno\-embedded\-data\fR" 4
.IX Item "-mno-embedded-data"
.PD
Allocate variables to the read-only data section first if possible, then
next in the small data section if possible, otherwise in data.  This gives
slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required
when executing, and thus may be preferred for some embedded systems.
.IP "\fB\-muninit\-const\-in\-rodata\fR" 4
.IX Item "-muninit-const-in-rodata"
.PD 0
.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4
.IX Item "-mno-uninit-const-in-rodata"
.PD
Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section.
This option is only meaningful in conjunction with \fB\-membedded\-data\fR.
.IP "\fB\-mcode\-readable=\fR\fIsetting\fR" 4
.IX Item "-mcode-readable=setting"
Specify whether \s-1GCC\s0 may generate code that reads from executable sections.
There are three possible settings:
.RS 4
.IP "\fB\-mcode\-readable=yes\fR" 4
.IX Item "-mcode-readable=yes"
Instructions may freely access executable sections.  This is the
default setting.
.IP "\fB\-mcode\-readable=pcrel\fR" 4
.IX Item "-mcode-readable=pcrel"
\&\s-1MIPS16\s0 PC-relative load instructions can access executable sections,
but other instructions must not do so.  This option is useful on 4KSc
and 4KSd processors when the code TLBs have the Read Inhibit bit set.
It is also useful on processors that can be configured to have a dual
instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically
redirect PC-relative loads to the instruction \s-1RAM\s0.
.IP "\fB\-mcode\-readable=no\fR" 4
.IX Item "-mcode-readable=no"
Instructions must not access executable sections.  This option can be
useful on targets that are configured to have a dual instruction/data
\&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect
PC-relative loads to the instruction \s-1RAM\s0.
.RE
.RS 4
.RE
.IP "\fB\-msplit\-addresses\fR" 4
.IX Item "-msplit-addresses"
.PD 0
.IP "\fB\-mno\-split\-addresses\fR" 4
.IX Item "-mno-split-addresses"
.PD
Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler
relocation operators.  This option has been superseded by
\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility.
.IP "\fB\-mexplicit\-relocs\fR" 4
.IX Item "-mexplicit-relocs"
.PD 0
.IP "\fB\-mno\-explicit\-relocs\fR" 4
.IX Item "-mno-explicit-relocs"
.PD
Use (do not use) assembler relocation operators when dealing with symbolic
addresses.  The alternative, selected by \fB\-mno\-explicit\-relocs\fR,
is to use assembler macros instead.
.Sp
\&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured
to use an assembler that supports relocation operators.
.IP "\fB\-mcheck\-zero\-division\fR" 4
.IX Item "-mcheck-zero-division"
.PD 0
.IP "\fB\-mno\-check\-zero\-division\fR" 4
.IX Item "-mno-check-zero-division"
.PD
Trap (do not trap) on integer division by zero.
.Sp
The default is \fB\-mcheck\-zero\-division\fR.
.IP "\fB\-mdivide\-traps\fR" 4
.IX Item "-mdivide-traps"
.PD 0
.IP "\fB\-mdivide\-breaks\fR" 4
.IX Item "-mdivide-breaks"
.PD
\&\s-1MIPS\s0 systems check for division by zero by generating either a
conditional trap or a break instruction.  Using traps results in
smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later.  Also, some
versions of the Linux kernel have a bug that prevents trap from
generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR).  Use \fB\-mdivide\-traps\fR to
allow conditional traps on architectures that support them and
\&\fB\-mdivide\-breaks\fR to force the use of breaks.
.Sp
The default is usually \fB\-mdivide\-traps\fR, but this can be
overridden at configure time using \fB\-\-with\-divide=breaks\fR.
Divide-by-zero checks can be completely disabled using
\&\fB\-mno\-check\-zero\-division\fR.
.IP "\fB\-mmemcpy\fR" 4
.IX Item "-mmemcpy"
.PD 0
.IP "\fB\-mno\-memcpy\fR" 4
.IX Item "-mno-memcpy"
.PD
Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block
moves.  The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline
most constant-sized copies.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.IP "\fB\-mno\-long\-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction.  Calling
functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller
and callee to be in the same 256 megabyte segment.
.Sp
This option has no effect on abicalls code.  The default is
\&\fB\-mno\-long\-calls\fR.
.IP "\fB\-mmad\fR" 4
.IX Item "-mmad"
.PD 0
.IP "\fB\-mno\-mad\fR" 4
.IX Item "-mno-mad"
.PD
Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR
instructions, as provided by the R4650 \s-1ISA\s0.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mno\-fused\-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Enable (disable) use of the floating point multiply-accumulate
instructions, when they are available.  The default is
\&\fB\-mfused\-madd\fR.
.Sp
When multiply-accumulate instructions are used, the intermediate
product is calculated to infinite precision and is not subject to
the \s-1FCSR\s0 Flush to Zero bit.  This may be undesirable in some
circumstances.
.IP "\fB\-nocpp\fR" 4
.IX Item "-nocpp"
Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user
assembler files (with a \fB.s\fR suffix) when assembling them.
.IP "\fB\-mfix\-r4000\fR" 4
.IX Item "-mfix-r4000"
.PD 0
.IP "\fB\-mno\-fix\-r4000\fR" 4
.IX Item "-mno-fix-r4000"
.PD
Work around certain R4000 \s-1CPU\s0 errata:
.RS 4
.IP "\-" 4
A double-word or a variable shift may give an incorrect result if executed
immediately after starting an integer division.
.IP "\-" 4
A double-word or a variable shift may give an incorrect result if executed
while an integer multiplication is in progress.
.IP "\-" 4
An integer division may give an incorrect result if started in a delay slot
of a taken branch or a jump.
.RE
.RS 4
.RE
.IP "\fB\-mfix\-r4400\fR" 4
.IX Item "-mfix-r4400"
.PD 0
.IP "\fB\-mno\-fix\-r4400\fR" 4
.IX Item "-mno-fix-r4400"
.PD
Work around certain R4400 \s-1CPU\s0 errata:
.RS 4
.IP "\-" 4
A double-word or a variable shift may give an incorrect result if executed
immediately after starting an integer division.
.RE
.RS 4
.RE
.IP "\fB\-mfix\-vr4120\fR" 4
.IX Item "-mfix-vr4120"
.PD 0
.IP "\fB\-mno\-fix\-vr4120\fR" 4
.IX Item "-mno-fix-vr4120"
.PD
Work around certain \s-1VR4120\s0 errata:
.RS 4
.IP "\-" 4
\&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result.
.IP "\-" 4
\&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one
of the operands is negative.
.RE
.RS 4
.Sp
The workarounds for the division errata rely on special functions in
\&\fIlibgcc.a\fR.  At present, these functions are only provided by
the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations.
.Sp
Other \s-1VR4120\s0 errata require a nop to be inserted between certain pairs of
instructions.  These errata are handled by the assembler, not by \s-1GCC\s0 itself.
.RE
.IP "\fB\-mfix\-vr4130\fR" 4
.IX Item "-mfix-vr4130"
Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata.  The
workarounds are implemented by the assembler rather than by \s-1GCC\s0,
although \s-1GCC\s0 will avoid using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the
\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR
instructions are available instead.
.IP "\fB\-mfix\-sb1\fR" 4
.IX Item "-mfix-sb1"
.PD 0
.IP "\fB\-mno\-fix\-sb1\fR" 4
.IX Item "-mno-fix-sb1"
.PD
Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata.
(This flag currently works around the \s-1SB\-1\s0 revision 2
\&\*(L"F1\*(R" and \*(L"F2\*(R" floating point errata.)
.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4
.IX Item "-mflush-func=func"
.PD 0
.IP "\fB\-mno\-flush\-func\fR" 4
.IX Item "-mno-flush-func"
.PD
Specifies the function to call to flush the I and D caches, or to not
call any such function.  If called, the function must take the same
arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the
memory range for which the cache is being flushed, the size of the
memory range, and the number 3 (to flush both caches).  The default
depends on the target \s-1GCC\s0 was configured for, but commonly is either
\&\fB_flush_func\fR or \fB_\|_cpu_flush\fR.
.IP "\fBmbranch\-cost=\fR\fInum\fR" 4
.IX Item "mbranch-cost=num"
Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions.
This cost is only a heuristic and is not guaranteed to produce
consistent results across releases.  A zero cost redundantly selects
the default, which is based on the \fB\-mtune\fR setting.
.IP "\fB\-mbranch\-likely\fR" 4
.IX Item "-mbranch-likely"
.PD 0
.IP "\fB\-mno\-branch\-likely\fR" 4
.IX Item "-mno-branch-likely"
.PD
Enable or disable use of Branch Likely instructions, regardless of the
default for the selected architecture.  By default, Branch Likely
instructions may be generated if they are supported by the selected
architecture.  An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures
and processors which implement those architectures; for those, Branch
Likely instructions will not be generated by default because the \s-1MIPS32\s0
and \s-1MIPS64\s0 architectures specifically deprecate their use.
.IP "\fB\-mfp\-exceptions\fR" 4
.IX Item "-mfp-exceptions"
.PD 0
.IP "\fB\-mno\-fp\-exceptions\fR" 4
.IX Item "-mno-fp-exceptions"
.PD
Specifies whether \s-1FP\s0 exceptions are enabled.  This affects how we schedule
\&\s-1FP\s0 instructions for some processors.  The default is that \s-1FP\s0 exceptions are
enabled.
.Sp
For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting
64\-bit code, then we can use both \s-1FP\s0 pipes.  Otherwise, we can only use one
\&\s-1FP\s0 pipe.
.IP "\fB\-mvr4130\-align\fR" 4
.IX Item "-mvr4130-align"
.PD 0
.IP "\fB\-mno\-vr4130\-align\fR" 4
.IX Item "-mno-vr4130-align"
.PD
The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two
instructions together if the first one is 8\-byte aligned.  When this
option is enabled, \s-1GCC\s0 will align pairs of instructions that it
thinks should execute in parallel.
.Sp
This option only has an effect when optimizing for the \s-1VR4130\s0.
It normally makes code faster, but at the expense of making it bigger.
It is enabled by default at optimization level \fB\-O3\fR.
.PP
\fI\s-1MMIX\s0 Options\fR
.IX Subsection "MMIX Options"
.PP
These options are defined for the \s-1MMIX:\s0
.IP "\fB\-mlibfuncs\fR" 4
.IX Item "-mlibfuncs"
.PD 0
.IP "\fB\-mno\-libfuncs\fR" 4
.IX Item "-mno-libfuncs"
.PD
Specify that intrinsic library functions are being compiled, passing all
values in registers, no matter the size.
.IP "\fB\-mepsilon\fR" 4
.IX Item "-mepsilon"
.PD 0
.IP "\fB\-mno\-epsilon\fR" 4
.IX Item "-mno-epsilon"
.PD
Generate floating-point comparison instructions that compare with respect
to the \f(CW\*(C`rE\*(C'\fR epsilon register.
.IP "\fB\-mabi=mmixware\fR" 4
.IX Item "-mabi=mmixware"
.PD 0
.IP "\f