|(1) for more information.
.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4
.IX Item "-bundle_loader executable"
This option specifies the \fIexecutable\fR that will be loading the build
output file being linked.  See man \fIld\fR\|(1) for more information.
.IP "\fB\-dynamiclib\fR" 4
.IX Item "-dynamiclib"
When passed this option, \s-1GCC\s0 will produce a dynamic library instead of
an executable when linking, using the Darwin \fIlibtool\fR command.
.IP "\fB\-force_cpusubtype_ALL\fR" 4
.IX Item "-force_cpusubtype_ALL"
This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of
one controlled by the \fB\-mcpu\fR or \fB\-march\fR option.
.IP "\fB\-allowable_client\fR  \fIclient_name\fR" 4
.IX Item "-allowable_client  client_name"
.PD 0
.IP "\fB\-client_name\fR" 4
.IX Item "-client_name"
.IP "\fB\-compatibility_version\fR" 4
.IX Item "-compatibility_version"
.IP "\fB\-current_version\fR" 4
.IX Item "-current_version"
.IP "\fB\-dead_strip\fR" 4
.IX Item "-dead_strip"
.IP "\fB\-dependency\-file\fR" 4
.IX Item "-dependency-file"
.IP "\fB\-dylib_file\fR" 4
.IX Item "-dylib_file"
.IP "\fB\-dylinker_install_name\fR" 4
.IX Item "-dylinker_install_name"
.IP "\fB\-dynamic\fR" 4
.IX Item "-dynamic"
.IP "\fB\-exported_symbols_list\fR" 4
.IX Item "-exported_symbols_list"
.IP "\fB\-filelist\fR" 4
.IX Item "-filelist"
.IP "\fB\-flat_namespace\fR" 4
.IX Item "-flat_namespace"
.IP "\fB\-force_flat_namespace\fR" 4
.IX Item "-force_flat_namespace"
.IP "\fB\-headerpad_max_install_names\fR" 4
.IX Item "-headerpad_max_install_names"
.IP "\fB\-image_base\fR" 4
.IX Item "-image_base"
.IP "\fB\-init\fR" 4
.IX Item "-init"
.IP "\fB\-install_name\fR" 4
.IX Item "-install_name"
.IP "\fB\-keep_private_externs\fR" 4
.IX Item "-keep_private_externs"
.IP "\fB\-multi_module\fR" 4
.IX Item "-multi_module"
.IP "\fB\-multiply_defined\fR" 4
.IX Item "-multiply_defined"
.IP "\fB\-multiply_defined_unused\fR" 4
.IX Item "-multiply_defined_unused"
.IP "\fB\-noall_load\fR" 4
.IX Item "-noall_load"
.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4
.IX Item "-no_dead_strip_inits_and_terms"
.IP "\fB\-nofixprebinding\fR" 4
.IX Item "-nofixprebinding"
.IP "\fB\-nomultidefs\fR" 4
.IX Item "-nomultidefs"
.IP "\fB\-noprebind\fR" 4
.IX Item "-noprebind"
.IP "\fB\-noseglinkedit\fR" 4
.IX Item "-noseglinkedit"
.IP "\fB\-pagezero_size\fR" 4
.IX Item "-pagezero_size"
.IP "\fB\-prebind\fR" 4
.IX Item "-prebind"
.IP "\fB\-prebind_all_twolevel_modules\fR" 4
.IX Item "-prebind_all_twolevel_modules"
.IP "\fB\-private_bundle\fR" 4
.IX Item "-private_bundle"
.IP "\fB\-read_only_relocs\fR" 4
.IX Item "-read_only_relocs"
.IP "\fB\-sectalign\fR" 4
.IX Item "-sectalign"
.IP "\fB\-sectobjectsymbols\fR" 4
.IX Item "-sectobjectsymbols"
.IP "\fB\-whyload\fR" 4
.IX Item "-whyload"
.IP "\fB\-seg1addr\fR" 4
.IX Item "-seg1addr"
.IP "\fB\-sectcreate\fR" 4
.IX Item "-sectcreate"
.IP "\fB\-sectobjectsymbols\fR" 4
.IX Item "-sectobjectsymbols"
.IP "\fB\-sectorder\fR" 4
.IX Item "-sectorder"
.IP "\fB\-segaddr\fR" 4
.IX Item "-segaddr"
.IP "\fB\-segs_read_only_addr\fR" 4
.IX Item "-segs_read_only_addr"
.IP "\fB\-segs_read_write_addr\fR" 4
.IX Item "-segs_read_write_addr"
.IP "\fB\-seg_addr_table\fR" 4
.IX Item "-seg_addr_table"
.IP "\fB\-seg_addr_table_filename\fR" 4
.IX Item "-seg_addr_table_filename"
.IP "\fB\-seglinkedit\fR" 4
.IX Item "-seglinkedit"
.IP "\fB\-segprot\fR" 4
.IX Item "-segprot"
.IP "\fB\-segs_read_only_addr\fR" 4
.IX Item "-segs_read_only_addr"
.IP "\fB\-segs_read_write_addr\fR" 4
.IX Item "-segs_read_write_addr"
.IP "\fB\-single_module\fR" 4
.IX Item "-single_module"
.IP "\fB\-static\fR" 4
.IX Item "-static"
.IP "\fB\-sub_library\fR" 4
.IX Item "-sub_library"
.IP "\fB\-sub_umbrella\fR" 4
.IX Item "-sub_umbrella"
.IP "\fB\-twolevel_namespace\fR" 4
.IX Item "-twolevel_namespace"
.IP "\fB\-umbrella\fR" 4
.IX Item "-umbrella"
.IP "\fB\-undefined\fR" 4
.IX Item "-undefined"
.IP "\fB\-unexported_symbols_list\fR" 4
.IX Item "-unexported_symbols_list"
.IP "\fB\-weak_reference_mismatches\fR" 4
.IX Item "-weak_reference_mismatches"
.IP "\fB\-whatsloaded\fR" 4
.IX Item "-whatsloaded"
.PD
These options are passed to the Darwin linker.  The Darwin linker man page
describes them in detail.
.PP
\fI\s-1DEC\s0 Alpha Options\fR
.IX Subsection "DEC Alpha Options"
.PP
These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations:
.IP "\fB\-mno\-soft\-float\fR" 4
.IX Item "-mno-soft-float"
.PD 0
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
.PD
Use (do not use) the hardware floating-point instructions for
floating-point operations.  When \fB\-msoft\-float\fR is specified,
functions in \fIlibgcc.a\fR will be used to perform floating-point
operations.  Unless they are replaced by routines that emulate the
floating-point operations, or compiled in such a way as to call such
emulations routines, these routines will issue floating-point
operations.   If you are compiling for an Alpha without floating-point
operations, you must ensure that the library is built so as not to call
them.
.Sp
Note that Alpha implementations without floating-point operations are
required to have floating-point registers.
.IP "\fB\-mfp\-reg\fR" 4
.IX Item "-mfp-reg"
.PD 0
.IP "\fB\-mno\-fp\-regs\fR" 4
.IX Item "-mno-fp-regs"
.PD
Generate code that uses (does not use) the floating-point register set.
\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR.  If the floating-point
register set is not used, floating point operands are passed in integer
registers as if they were integers and floating-point results are passed
in \f(CW$0\fR instead of \f(CW$f0\fR.  This is a non-standard calling sequence,
so any function with a floating-point argument or return value called by code
compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that
option.
.Sp
A typical use of this option is building a kernel that does not use,
and hence need not save and restore, any floating-point registers.
.IP "\fB\-mieee\fR" 4
.IX Item "-mieee"
The Alpha architecture implements floating-point hardware optimized for
maximum performance.  It is mostly compliant with the \s-1IEEE\s0 floating
point standard.  However, for full compliance, software assistance is
required.  This option generates code fully \s-1IEEE\s0 compliant code
\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below).
If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is
defined during compilation.  The resulting code is less efficient but is
able to correctly support denormalized numbers and exceptional \s-1IEEE\s0
values such as not-a-number and plus/minus infinity.  Other Alpha
compilers call this option \fB\-ieee_with_no_inexact\fR.
.IP "\fB\-mieee\-with\-inexact\fR" 4
.IX Item "-mieee-with-inexact"
This is like \fB\-mieee\fR except the generated code also maintains
the \s-1IEEE\s0 \fIinexact-flag\fR.  Turning on this option causes the
generated code to implement fully-compliant \s-1IEEE\s0 math.  In addition to
\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor
macro.  On some Alpha implementations the resulting code may execute
significantly slower than the code generated by default.  Since there is
very little code that depends on the \fIinexact-flag\fR, you should
normally not specify this option.  Other Alpha compilers call this
option \fB\-ieee_with_inexact\fR.
.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4
.IX Item "-mfp-trap-mode=trap-mode"
This option controls what floating-point related traps are enabled.
Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR.
The trap mode can be set to one of four values:
.RS 4
.IP "\fBn\fR" 4
.IX Item "n"
This is the default (normal) setting.  The only traps that are enabled
are the ones that cannot be disabled in software (e.g., division by zero
trap).
.IP "\fBu\fR" 4
.IX Item "u"
In addition to the traps enabled by \fBn\fR, underflow traps are enabled
as well.
.IP "\fBsu\fR" 4
.IX Item "su"
Like \fBu\fR, but the instructions are marked to be safe for software
completion (see Alpha architecture manual for details).
.IP "\fBsui\fR" 4
.IX Item "sui"
Like \fBsu\fR, but inexact traps are enabled as well.
.RE
.RS 4
.RE
.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4
.IX Item "-mfp-rounding-mode=rounding-mode"
Selects the \s-1IEEE\s0 rounding mode.  Other Alpha compilers call this option
\&\fB\-fprm\fR \fIrounding-mode\fR.  The \fIrounding-mode\fR can be one
of:
.RS 4
.IP "\fBn\fR" 4
.IX Item "n"
Normal \s-1IEEE\s0 rounding mode.  Floating point numbers are rounded towards
the nearest machine number or towards the even machine number in case
of a tie.
.IP "\fBm\fR" 4
.IX Item "m"
Round towards minus infinity.
.IP "\fBc\fR" 4
.IX Item "c"
Chopped rounding mode.  Floating point numbers are rounded towards zero.
.IP "\fBd\fR" 4
.IX Item "d"
Dynamic rounding mode.  A field in the floating point control register
(\fIfpcr\fR, see Alpha architecture reference manual) controls the
rounding mode in effect.  The C library initializes this register for
rounding towards plus infinity.  Thus, unless your program modifies the
\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity.
.RE
.RS 4
.RE
.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4
.IX Item "-mtrap-precision=trap-precision"
In the Alpha architecture, floating point traps are imprecise.  This
means without software assistance it is impossible to recover from a
floating trap and program execution normally needs to be terminated.
\&\s-1GCC\s0 can generate code that can assist operating system trap handlers
in determining the exact location that caused a floating point trap.
Depending on the requirements of an application, different levels of
precisions can be selected:
.RS 4
.IP "\fBp\fR" 4
.IX Item "p"
Program precision.  This option is the default and means a trap handler
can only identify which program caused a floating point exception.
.IP "\fBf\fR" 4
.IX Item "f"
Function precision.  The trap handler can determine the function that
caused a floating point exception.
.IP "\fBi\fR" 4
.IX Item "i"
Instruction precision.  The trap handler can determine the exact
instruction that caused a floating point exception.
.RE
.RS 4
.Sp
Other Alpha compilers provide the equivalent options called
\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR.
.RE
.IP "\fB\-mieee\-conformant\fR" 4
.IX Item "-mieee-conformant"
This option marks the generated code as \s-1IEEE\s0 conformant.  You must not
use this option unless you also specify \fB\-mtrap\-precision=i\fR and either
\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR.  Its only effect
is to emit the line \fB.eflag 48\fR in the function prologue of the
generated assembly file.  Under \s-1DEC\s0 Unix, this has the effect that
IEEE-conformant math library routines will be linked in.
.IP "\fB\-mbuild\-constants\fR" 4
.IX Item "-mbuild-constants"
Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to
see if it can construct it from smaller constants in two or three
instructions.  If it cannot, it will output the constant as a literal and
generate code to load it from the data segment at runtime.
.Sp
Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants
using code, even if it takes more instructions (the maximum is six).
.Sp
You would typically use this option to build a shared library dynamic
loader.  Itself a shared library, it must relocate itself in memory
before it can find the variables and constants in its own data segment.
.IP "\fB\-malpha\-as\fR" 4
.IX Item "-malpha-as"
.PD 0
.IP "\fB\-mgas\fR" 4
.IX Item "-mgas"
.PD
Select whether to generate code to be assembled by the vendor-supplied
assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR.
.IP "\fB\-mbwx\fR" 4
.IX Item "-mbwx"
.PD 0
.IP "\fB\-mno\-bwx\fR" 4
.IX Item "-mno-bwx"
.IP "\fB\-mcix\fR" 4
.IX Item "-mcix"
.IP "\fB\-mno\-cix\fR" 4
.IX Item "-mno-cix"
.IP "\fB\-mfix\fR" 4
.IX Item "-mfix"
.IP "\fB\-mno\-fix\fR" 4
.IX Item "-mno-fix"
.IP "\fB\-mmax\fR" 4
.IX Item "-mmax"
.IP "\fB\-mno\-max\fR" 4
.IX Item "-mno-max"
.PD
Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0,
\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets.  The default is to use the instruction
sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that
of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified.
.IP "\fB\-mfloat\-vax\fR" 4
.IX Item "-mfloat-vax"
.PD 0
.IP "\fB\-mfloat\-ieee\fR" 4
.IX Item "-mfloat-ieee"
.PD
Generate code that uses (does not use) \s-1VAX\s0 F and G floating point
arithmetic instead of \s-1IEEE\s0 single and double precision.
.IP "\fB\-mexplicit\-relocs\fR" 4
.IX Item "-mexplicit-relocs"
.PD 0
.IP "\fB\-mno\-explicit\-relocs\fR" 4
.IX Item "-mno-explicit-relocs"
.PD
Older Alpha assemblers provided no way to generate symbol relocations
except via assembler macros.  Use of these macros does not allow
optimal instruction scheduling.  \s-1GNU\s0 binutils as of version 2.12
supports a new syntax that allows the compiler to explicitly mark
which relocations should apply to which instructions.  This option
is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of
the assembler when it is built and sets the default accordingly.
.IP "\fB\-msmall\-data\fR" 4
.IX Item "-msmall-data"
.PD 0
.IP "\fB\-mlarge\-data\fR" 4
.IX Item "-mlarge-data"
.PD
When \fB\-mexplicit\-relocs\fR is in effect, static data is
accessed via \fIgp-relative\fR relocations.  When \fB\-msmall\-data\fR
is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR
(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via
16\-bit relocations off of the \f(CW$gp\fR register.  This limits the
size of the small data area to 64KB, but allows the variables to be
directly accessed via a single instruction.
.Sp
The default is \fB\-mlarge\-data\fR.  With this option the data area
is limited to just below 2GB.  Programs that require more than 2GB of
data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the
heap instead of in the program's data segment.
.Sp
When generating code for shared libraries, \fB\-fpic\fR implies
\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR.
.IP "\fB\-msmall\-text\fR" 4
.IX Item "-msmall-text"
.PD 0
.IP "\fB\-mlarge\-text\fR" 4
.IX Item "-mlarge-text"
.PD
When \fB\-msmall\-text\fR is used, the compiler assumes that the
code of the entire program (or shared library) fits in 4MB, and is
thus reachable with a branch instruction.  When \fB\-msmall\-data\fR
is used, the compiler can assume that all local symbols share the
same \f(CW$gp\fR value, and thus reduce the number of instructions
required for a function call from 4 to 1.
.Sp
The default is \fB\-mlarge\-text\fR.
.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set the instruction set and instruction scheduling parameters for
machine type \fIcpu_type\fR.  You can specify either the \fB\s-1EV\s0\fR
style name or the corresponding chip number.  \s-1GCC\s0 supports scheduling
parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will
choose the default values for the instruction set from the processor
you specify.  If you do not specify a processor type, \s-1GCC\s0 will default
to the processor on which the compiler was built.
.Sp
Supported values for \fIcpu_type\fR are
.RS 4
.IP "\fBev4\fR" 4
.IX Item "ev4"
.PD 0
.IP "\fBev45\fR" 4
.IX Item "ev45"
.IP "\fB21064\fR" 4
.IX Item "21064"
.PD
Schedules as an \s-1EV4\s0 and has no instruction set extensions.
.IP "\fBev5\fR" 4
.IX Item "ev5"
.PD 0
.IP "\fB21164\fR" 4
.IX Item "21164"
.PD
Schedules as an \s-1EV5\s0 and has no instruction set extensions.
.IP "\fBev56\fR" 4
.IX Item "ev56"
.PD 0
.IP "\fB21164a\fR" 4
.IX Item "21164a"
.PD
Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension.
.IP "\fBpca56\fR" 4
.IX Item "pca56"
.PD 0
.IP "\fB21164pc\fR" 4
.IX Item "21164pc"
.IP "\fB21164PC\fR" 4
.IX Item "21164PC"
.PD
Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions.
.IP "\fBev6\fR" 4
.IX Item "ev6"
.PD 0
.IP "\fB21264\fR" 4
.IX Item "21264"
.PD
Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
.IP "\fBev67\fR" 4
.IX Item "ev67"
.PD 0
.IP "\fB21264a\fR" 4
.IX Item "21264a"
.PD
Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
.RE
.RS 4
.RE
.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set only the instruction scheduling parameters for machine type
\&\fIcpu_type\fR.  The instruction set is not changed.
.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4
.IX Item "-mmemory-latency=time"
Sets the latency the scheduler should assume for typical memory
references as seen by the application.  This number is highly
dependent on the memory access patterns used by the application
and the size of the external cache on the machine.
.Sp
Valid options for \fItime\fR are
.RS 4
.IP "\fInumber\fR" 4
.IX Item "number"
A decimal number representing clock cycles.
.IP "\fBL1\fR" 4
.IX Item "L1"
.PD 0
.IP "\fBL2\fR" 4
.IX Item "L2"
.IP "\fBL3\fR" 4
.IX Item "L3"
.IP "\fBmain\fR" 4
.IX Item "main"
.PD
The compiler contains estimates of the number of clock cycles for
\&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches
(also called Dcache, Scache, and Bcache), as well as to main memory.
Note that L3 is only valid for \s-1EV5\s0.
.RE
.RS 4
.RE
.PP
\fI\s-1DEC\s0 Alpha/VMS Options\fR
.IX Subsection "DEC Alpha/VMS Options"
.PP
These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations:
.IP "\fB\-mvms\-return\-codes\fR" 4
.IX Item "-mvms-return-codes"
Return \s-1VMS\s0 condition codes from main.  The default is to return \s-1POSIX\s0
style condition (e.g. error) codes.
.PP
\fI\s-1FRV\s0 Options\fR
.IX Subsection "FRV Options"
.IP "\fB\-mgpr\-32\fR" 4
.IX Item "-mgpr-32"
Only use the first 32 general purpose registers.
.IP "\fB\-mgpr\-64\fR" 4
.IX Item "-mgpr-64"
Use all 64 general purpose registers.
.IP "\fB\-mfpr\-32\fR" 4
.IX Item "-mfpr-32"
Use only the first 32 floating point registers.
.IP "\fB\-mfpr\-64\fR" 4
.IX Item "-mfpr-64"
Use all 64 floating point registers
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
Use hardware instructions for floating point operations.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Use library routines for floating point operations.
.IP "\fB\-malloc\-cc\fR" 4
.IX Item "-malloc-cc"
Dynamically allocate condition code registers.
.IP "\fB\-mfixed\-cc\fR" 4
.IX Item "-mfixed-cc"
Do not try to dynamically allocate condition code registers, only
use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR.
.IP "\fB\-mdword\fR" 4
.IX Item "-mdword"
Change \s-1ABI\s0 to use double word insns.
.IP "\fB\-mno\-dword\fR" 4
.IX Item "-mno-dword"
Do not use double word instructions.
.IP "\fB\-mdouble\fR" 4
.IX Item "-mdouble"
Use floating point double instructions.
.IP "\fB\-mno\-double\fR" 4
.IX Item "-mno-double"
Do not use floating point double instructions.
.IP "\fB\-mmedia\fR" 4
.IX Item "-mmedia"
Use media instructions.
.IP "\fB\-mno\-media\fR" 4
.IX Item "-mno-media"
Do not use media instructions.
.IP "\fB\-mmuladd\fR" 4
.IX Item "-mmuladd"
Use multiply and add/subtract instructions.
.IP "\fB\-mno\-muladd\fR" 4
.IX Item "-mno-muladd"
Do not use multiply and add/subtract instructions.
.IP "\fB\-mfdpic\fR" 4
.IX Item "-mfdpic"
Select the \s-1FDPIC\s0 \s-1ABI\s0, that uses function descriptors to represent
pointers to functions.  Without any PIC/PIE\-related options, it
implies \fB\-fPIE\fR.  With \fB\-fpic\fR or \fB\-fpie\fR, it
assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the
\&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets
are computed with 32 bits.
With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR.
.IP "\fB\-minline\-plt\fR" 4
.IX Item "-minline-plt"
Enable inlining of \s-1PLT\s0 entries in function calls to functions that are
not known to bind locally.  It has no effect without \fB\-mfdpic\fR.
It's enabled by default if optimizing for speed and compiling for
shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an
optimization option such as \fB\-O3\fR or above is present in the
command line.
.IP "\fB\-mTLS\fR" 4
.IX Item "-mTLS"
Assume a large \s-1TLS\s0 segment when generating thread-local code.
.IP "\fB\-mtls\fR" 4
.IX Item "-mtls"
Do not assume a large \s-1TLS\s0 segment when generating thread-local code.
.IP "\fB\-mgprel\-ro\fR" 4
.IX Item "-mgprel-ro"
Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data
that is known to be in read-only sections.  It's enabled by default,
except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help
make the global offset table smaller, it trades 1 instruction for 4.
With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4,
one of which may be shared by multiple symbols, and it avoids the need
for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a
win.  If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it.
.IP "\fB\-multilib\-library\-pic\fR" 4
.IX Item "-multilib-library-pic"
Link with the (library, not \s-1FD\s0) pic libraries.  It's implied by
\&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and
\&\fB\-fpic\fR without \fB\-mfdpic\fR.  You should never have to use
it explicitly.
.IP "\fB\-mlinked\-fp\fR" 4
.IX Item "-mlinked-fp"
Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever
a stack frame is allocated.  This option is enabled by default and can
be disabled with \fB\-mno\-linked\-fp\fR.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
Use indirect addressing to call functions outside the current
compilation unit.  This allows the functions to be placed anywhere
within the 32\-bit address space.
.IP "\fB\-malign\-labels\fR" 4
.IX Item "-malign-labels"
Try to align labels to an 8\-byte boundary by inserting nops into the
previous packet.  This option only has an effect when \s-1VLIW\s0 packing
is enabled.  It doesn't create new packets; it merely adds nops to
existing ones.
.IP "\fB\-mlibrary\-pic\fR" 4
.IX Item "-mlibrary-pic"
Generate position-independent \s-1EABI\s0 code.
.IP "\fB\-macc\-4\fR" 4
.IX Item "-macc-4"
Use only the first four media accumulator registers.
.IP "\fB\-macc\-8\fR" 4
.IX Item "-macc-8"
Use all eight media accumulator registers.
.IP "\fB\-mpack\fR" 4
.IX Item "-mpack"
Pack \s-1VLIW\s0 instructions.
.IP "\fB\-mno\-pack\fR" 4
.IX Item "-mno-pack"
Do not pack \s-1VLIW\s0 instructions.
.IP "\fB\-mno\-eflags\fR" 4
.IX Item "-mno-eflags"
Do not mark \s-1ABI\s0 switches in e_flags.
.IP "\fB\-mcond\-move\fR" 4
.IX Item "-mcond-move"
Enable the use of conditional-move instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-cond\-move\fR" 4
.IX Item "-mno-cond-move"
Disable the use of conditional-move instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mscc\fR" 4
.IX Item "-mscc"
Enable the use of conditional set instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-scc\fR" 4
.IX Item "-mno-scc"
Disable the use of conditional set instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mcond\-exec\fR" 4
.IX Item "-mcond-exec"
Enable the use of conditional execution (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-cond\-exec\fR" 4
.IX Item "-mno-cond-exec"
Disable the use of conditional execution.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mvliw\-branch\fR" 4
.IX Item "-mvliw-branch"
Run a pass to pack branches into \s-1VLIW\s0 instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-vliw\-branch\fR" 4
.IX Item "-mno-vliw-branch"
Do not run a pass to pack branches into \s-1VLIW\s0 instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mmulti\-cond\-exec\fR" 4
.IX Item "-mmulti-cond-exec"
Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution
(default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-multi\-cond\-exec\fR" 4
.IX Item "-mno-multi-cond-exec"
Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mnested\-cond\-exec\fR" 4
.IX Item "-mnested-cond-exec"
Enable nested conditional execution optimizations (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-nested\-cond\-exec\fR" 4
.IX Item "-mno-nested-cond-exec"
Disable nested conditional execution optimizations.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-moptimize\-membar\fR" 4
.IX Item "-moptimize-membar"
This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the
compiler generated code.  It is enabled by default.
.IP "\fB\-mno\-optimize\-membar\fR" 4
.IX Item "-mno-optimize-membar"
This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR
instructions from the generated code.
.IP "\fB\-mtomcat\-stats\fR" 4
.IX Item "-mtomcat-stats"
Cause gas to print out tomcat statistics.
.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
.IX Item "-mcpu=cpu"
Select the processor type for which to generate code.  Possible values are
\&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR,
\&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR.
.PP
\fIGNU/Linux Options\fR
.IX Subsection "GNU/Linux Options"
.PP
These \fB\-m\fR options are defined for GNU/Linux targets:
.IP "\fB\-mglibc\fR" 4
.IX Item "-mglibc"
Use the \s-1GNU\s0 C library instead of uClibc.  This is the default except
on \fB*\-*\-linux\-*uclibc*\fR targets.
.IP "\fB\-muclibc\fR" 4
.IX Item "-muclibc"
Use uClibc instead of the \s-1GNU\s0 C library.  This is the default on
\&\fB*\-*\-linux\-*uclibc*\fR targets.
.PP
\fIH8/300 Options\fR
.IX Subsection "H8/300 Options"
.PP
These \fB\-m\fR options are defined for the H8/300 implementations:
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Shorten some address references at link time, when possible; uses the
linker option \fB\-relax\fR.
.IP "\fB\-mh\fR" 4
.IX Item "-mh"
Generate code for the H8/300H.
.IP "\fB\-ms\fR" 4
.IX Item "-ms"
Generate code for the H8S.
.IP "\fB\-mn\fR" 4
.IX Item "-mn"
Generate code for the H8S and H8/300H in the normal mode.  This switch
must be used either with \fB\-mh\fR or \fB\-ms\fR.
.IP "\fB\-ms2600\fR" 4
.IX Item "-ms2600"
Generate code for the H8S/2600.  This switch must be used with \fB\-ms\fR.
.IP "\fB\-mint32\fR" 4
.IX Item "-mint32"
Make \f(CW\*(C`int\*(C'\fR data 32 bits by default.
.IP "\fB\-malign\-300\fR" 4
.IX Item "-malign-300"
On the H8/300H and H8S, use the same alignment rules as for the H8/300.
The default for the H8/300H and H8S is to align longs and floats on 4
byte boundaries.
\&\fB\-malign\-300\fR causes them to be aligned on 2 byte boundaries.
This option has no effect on the H8/300.
.PP
\fI\s-1HPPA\s0 Options\fR
.IX Subsection "HPPA Options"
.PP
These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers:
.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
.IX Item "-march=architecture-type"
Generate code for the specified architecture.  The choices for
\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0
1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors.  Refer to
\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper
architecture option for your machine.  Code compiled for lower numbered
architectures will run on higher numbered architectures, but not the
other way around.
.IP "\fB\-mpa\-risc\-1\-0\fR" 4
.IX Item "-mpa-risc-1-0"
.PD 0
.IP "\fB\-mpa\-risc\-1\-1\fR" 4
.IX Item "-mpa-risc-1-1"
.IP "\fB\-mpa\-risc\-2\-0\fR" 4
.IX Item "-mpa-risc-2-0"
.PD
Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively.
.IP "\fB\-mbig\-switch\fR" 4
.IX Item "-mbig-switch"
Generate code suitable for big switch tables.  Use this option only if
the assembler/linker complain about out of range branches within a switch
table.
.IP "\fB\-mjump\-in\-delay\fR" 4
.IX Item "-mjump-in-delay"
Fill delay slots of function calls with unconditional jump instructions
by modifying the return pointer for the function call to be the target
of the conditional jump.
.IP "\fB\-mdisable\-fpregs\fR" 4
.IX Item "-mdisable-fpregs"
Prevent floating point registers from being used in any manner.  This is
necessary for compiling kernels which perform lazy context switching of
floating point registers.  If you use this option and attempt to perform
floating point operations, the compiler will abort.
.IP "\fB\-mdisable\-indexing\fR" 4
.IX Item "-mdisable-indexing"
Prevent the compiler from using indexing address modes.  This avoids some
rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0.
.IP "\fB\-mno\-space\-regs\fR" 4
.IX Item "-mno-space-regs"
Generate code that assumes the target has no space registers.  This allows
\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes.
.Sp
Such code is suitable for level 0 \s-1PA\s0 systems and kernels.
.IP "\fB\-mfast\-indirect\-calls\fR" 4
.IX Item "-mfast-indirect-calls"
Generate code that assumes calls never cross space boundaries.  This
allows \s-1GCC\s0 to emit code which performs faster indirect calls.
.Sp
This option will not work in the presence of shared libraries or nested
functions.
.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator can not use.  This is
useful when compiling kernel code.  A register range is specified as
two registers separated by a dash.  Multiple register ranges can be
specified separated by a comma.
.IP "\fB\-mlong\-load\-store\fR" 4
.IX Item "-mlong-load-store"
Generate 3\-instruction load and store sequences as sometimes required by
the HP-UX 10 linker.  This is equivalent to the \fB+k\fR option to
the \s-1HP\s0 compilers.
.IP "\fB\-mportable\-runtime\fR" 4
.IX Item "-mportable-runtime"
Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems.
.IP "\fB\-mgas\fR" 4
.IX Item "-mgas"
Enable the use of assembler directives only \s-1GAS\s0 understands.
.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4
.IX Item "-mschedule=cpu-type"
Schedule code according to the constraints for the machine type
\&\fIcpu-type\fR.  The choices for \fIcpu-type\fR are \fB700\fR
\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR.  Refer
to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the
proper scheduling option for your machine.  The default scheduling is
\&\fB8000\fR.
.IP "\fB\-mlinker\-opt\fR" 4
.IX Item "-mlinker-opt"
Enable the optimization pass in the HP-UX linker.  Note this makes symbolic
debugging impossible.  It also triggers a bug in the HP-UX 8 and HP-UX 9
linkers in which they give bogus error messages when linking some programs.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not available for all \s-1HPPA\s0
targets.  Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation.  You must make
your own arrangements to provide suitable library functions for
cross-compilation.  The embedded target \fBhppa1.1\-*\-pro\fR
does provide software floating point support.
.Sp
\&\fB\-msoft\-float\fR changes the calling convention in the output file;
therefore, it is only useful if you compile \fIall\fR of a program with
this option.  In particular, you need to compile \fIlibgcc.a\fR, the
library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for
this to work.
.IP "\fB\-msio\fR" 4
.IX Item "-msio"
Generate the predefine, \f(CW\*(C`_SIO\*(C'\fR, for server \s-1IO\s0.  The default is
\&\fB\-mwsio\fR.  This generates the predefines, \f(CW\*(C`_\|_hp9000s700\*(C'\fR,
\&\f(CW\*(C`_\|_hp9000s700_\|_\*(C'\fR and \f(CW\*(C`_WSIO\*(C'\fR, for workstation \s-1IO\s0.  These
options are available under HP-UX and HI-UX.
.IP "\fB\-mgnu\-ld\fR" 4
.IX Item "-mgnu-ld"
Use \s-1GNU\s0 ld specific options.  This passes \fB\-shared\fR to ld when
building a shared library.  It is the default when \s-1GCC\s0 is configured,
explicitly or implicitly, with the \s-1GNU\s0 linker.  This option does not
have any affect on which ld is called, it only changes what parameters
are passed to that ld.  The ld that is called is determined by the
\&\fB\-\-with\-ld\fR configure option, \s-1GCC\s0's program search path, and
finally by the user's \fB\s-1PATH\s0\fR.  The linker used by \s-1GCC\s0 can be printed
using \fBwhich `gcc \-print\-prog\-name=ld`\fR.  This option is only available
on the 64 bit HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR.
.IP "\fB\-mhp\-ld\fR" 4
.IX Item "-mhp-ld"
Use \s-1HP\s0 ld specific options.  This passes \fB\-b\fR to ld when building
a shared library and passes \fB+Accept TypeMismatch\fR to ld on all
links.  It is the default when \s-1GCC\s0 is configured, explicitly or
implicitly, with the \s-1HP\s0 linker.  This option does not have any affect on
which ld is called, it only changes what parameters are passed to that
ld.  The ld that is called is determined by the \fB\-\-with\-ld\fR
configure option, \s-1GCC\s0's program search path, and finally by the user's
\&\fB\s-1PATH\s0\fR.  The linker used by \s-1GCC\s0 can be printed using \fBwhich
`gcc \-print\-prog\-name=ld`\fR.  This option is only available on the 64 bit
HP-UX \s-1GCC\s0, i.e. configured with \fBhppa*64*\-*\-hpux*\fR.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
Generate code that uses long call sequences.  This ensures that a call
is always able to reach linker generated stubs.  The default is to generate
long calls only when the distance from the call site to the beginning
of the function or translation unit, as the case may be, exceeds a
predefined limit set by the branch type being used.  The limits for
normal calls are 7,600,000 and 240,000 bytes, respectively for the
\&\s-1PA\s0 2.0 and \s-1PA\s0 1.X architectures.  Sibcalls are always limited at
240,000 bytes.
.Sp
Distances are measured from the beginning of functions when using the
\&\fB\-ffunction\-sections\fR option, or when using the \fB\-mgas\fR
and \fB\-mno\-portable\-runtime\fR options together under HP-UX with
the \s-1SOM\s0 linker.
.Sp
It is normally not desirable to use this option as it will degrade
performance.  However, it may be useful in large applications,
particularly when partial linking is used to build the application.
.Sp
The types of long calls used depends on the capabilities of the
assembler and linker, and the type of code being generated.  The
impact on systems that support long absolute calls, and long pic
symbol-difference or pc-relative calls should be relatively small.
However, an indirect call is used on 32\-bit \s-1ELF\s0 systems in pic code
and it is quite long.
.IP "\fB\-munix=\fR\fIunix-std\fR" 4
.IX Item "-munix=unix-std"
Generate compiler predefines and select a startfile for the specified
\&\s-1UNIX\s0 standard.  The choices for \fIunix-std\fR are \fB93\fR, \fB95\fR
and \fB98\fR.  \fB93\fR is supported on all HP-UX versions.  \fB95\fR
is available on HP-UX 10.10 and later.  \fB98\fR is available on HP-UX
11.11 and later.  The default values are \fB93\fR for HP-UX 10.00,
\&\fB95\fR for HP-UX 10.10 though to 11.00, and \fB98\fR for HP-UX 11.11
and later.
.Sp
\&\fB\-munix=93\fR provides the same predefines as \s-1GCC\s0 3.3 and 3.4.
\&\fB\-munix=95\fR provides additional predefines for \f(CW\*(C`XOPEN_UNIX\*(C'\fR
and \f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, and the startfile \fIunix95.o\fR.
\&\fB\-munix=98\fR provides additional predefines for \f(CW\*(C`_XOPEN_UNIX\*(C'\fR,
\&\f(CW\*(C`_XOPEN_SOURCE_EXTENDED\*(C'\fR, \f(CW\*(C`_INCLUDE_\|_STDC_A1_SOURCE\*(C'\fR and
\&\f(CW\*(C`_INCLUDE_XOPEN_SOURCE_500\*(C'\fR, and the startfile \fIunix98.o\fR.
.Sp
It is \fIimportant\fR to note that this option changes the interfaces
for various library routines.  It also affects the operational behavior
of the C library.  Thus, \fIextreme\fR care is needed in using this
option.
.Sp
Library code that is intended to operate with more than one \s-1UNIX\s0
standard must test, set and restore the variable \fI_\|_xpg4_extended_mask\fR
as appropriate.  Most \s-1GNU\s0 software doesn't provide this capability.
.IP "\fB\-nolibdld\fR" 4
.IX Item "-nolibdld"
Suppress the generation of link options to search libdld.sl when the
\&\fB\-static\fR option is specified on HP-UX 10 and later.
.IP "\fB\-static\fR" 4
.IX Item "-static"
The HP-UX implementation of setlocale in libc has a dependency on
libdld.sl.  There isn't an archive version of libdld.sl.  Thus,
when the \fB\-static\fR option is specified, special link options
are needed to resolve this dependency.
.Sp
On HP-UX 10 and later, the \s-1GCC\s0 driver adds the necessary options to
link with libdld.sl when the \fB\-static\fR option is specified.
This causes the resulting binary to be dynamic.  On the 64\-bit port,
the linkers generate dynamic binaries by default in any case.  The
\&\fB\-nolibdld\fR option can be used to prevent the \s-1GCC\s0 driver from
adding these link options.
.IP "\fB\-threads\fR" 4
.IX Item "-threads"
Add support for multithreading with the \fIdce thread\fR library
under HP-UX.  This option sets flags for both the preprocessor and
linker.
.PP
\fIIntel 386 and \s-1AMD\s0 x86\-64 Options\fR
.IX Subsection "Intel 386 and AMD x86-64 Options"
.PP
These \fB\-m\fR options are defined for the i386 and x86\-64 family of
computers:
.IP "\fB\-mtune=\fR\fIcpu-type\fR" 4
.IX Item "-mtune=cpu-type"
Tune to \fIcpu-type\fR everything applicable about the generated code, except
for the \s-1ABI\s0 and the set of available instructions.  The choices for
\&\fIcpu-type\fR are:
.RS 4
.IP "\fIgeneric\fR" 4
.IX Item "generic"
Produce code optimized for the most common \s-1IA32/AMD64/EM64T\s0 processors.
If you know the \s-1CPU\s0 on which your code will run, then you should use
the corresponding \fB\-mtune\fR option instead of
\&\fB\-mtune=generic\fR.  But, if you do not know exactly what \s-1CPU\s0 users
of your application will have, then you should use this option.
.Sp
As new processors are deployed in the marketplace, the behavior of this
option will change.  Therefore, if you upgrade to a newer version of
\&\s-1GCC\s0, the code generated option will change to reflect the processors
that were most common when that version of \s-1GCC\s0 was released.
.Sp
There is no \fB\-march=generic\fR option because \fB\-march\fR
indicates the instruction set the compiler can use, and there is no
generic instruction set applicable to all processors.  In contrast,
\&\fB\-mtune\fR indicates the processor (or, in this case, collection of
processors) for which the code is optimized.
.IP "\fInative\fR" 4
.IX Item "native"
This selects the \s-1CPU\s0 to tune for at compilation time by determining
the processor type of the compiling machine.  Using \fB\-mtune=native\fR
will produce code optimized for the local machine under the constraints
of the selected instruction set.  Using \fB\-march=native\fR will
enable all instruction subsets supported by the local machine (hence
the result might not run on different machines).
.IP "\fIi386\fR" 4
.IX Item "i386"
Original Intel's i386 \s-1CPU\s0.
.IP "\fIi486\fR" 4
.IX Item "i486"
Intel's i486 \s-1CPU\s0.  (No scheduling is implemented for this chip.)
.IP "\fIi586, pentium\fR" 4
.IX Item "i586, pentium"
Intel Pentium \s-1CPU\s0 with no \s-1MMX\s0 support.
.IP "\fIpentium-mmx\fR" 4
.IX Item "pentium-mmx"
Intel PentiumMMX \s-1CPU\s0 based on Pentium core with \s-1MMX\s0 instruction set support.
.IP "\fIpentiumpro\fR" 4
.IX Item "pentiumpro"
Intel PentiumPro \s-1CPU\s0.
.IP "\fIi686\fR" 4
.IX Item "i686"
Same as \f(CW\*(C`generic\*(C'\fR, but when used as \f(CW\*(C`march\*(C'\fR option, PentiumPro
instruction set will be used, so the code will run on all i686 family chips.
.IP "\fIpentium2\fR" 4
.IX Item "pentium2"
Intel Pentium2 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 instruction set support.
.IP "\fIpentium3, pentium3m\fR" 4
.IX Item "pentium3, pentium3m"
Intel Pentium3 \s-1CPU\s0 based on PentiumPro core with \s-1MMX\s0 and \s-1SSE\s0 instruction set
support.
.IP "\fIpentium-m\fR" 4
.IX Item "pentium-m"
Low power version of Intel Pentium3 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set
support.  Used by Centrino notebooks.
.IP "\fIpentium4, pentium4m\fR" 4
.IX Item "pentium4, pentium4m"
Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0 and \s-1SSE2\s0 instruction set support.
.IP "\fIprescott\fR" 4
.IX Item "prescott"
Improved version of Intel Pentium4 \s-1CPU\s0 with \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0 and \s-1SSE3\s0 instruction
set support.
.IP "\fInocona\fR" 4
.IX Item "nocona"
Improved version of Intel Pentium4 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0,
\&\s-1SSE2\s0 and \s-1SSE3\s0 instruction set support.
.IP "\fIcore2\fR" 4
.IX Item "core2"
Intel Core2 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0
instruction set support.
.IP "\fIk6\fR" 4
.IX Item "k6"
\&\s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 instruction set support.
.IP "\fIk6\-2, k6\-3\fR" 4
.IX Item "k6-2, k6-3"
Improved versions of \s-1AMD\s0 K6 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support.
.IP "\fIathlon, athlon-tbird\fR" 4
.IX Item "athlon, athlon-tbird"
\&\s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and \s-1SSE\s0 prefetch instructions
support.
.IP "\fIathlon\-4, athlon-xp, athlon-mp\fR" 4
.IX Item "athlon-4, athlon-xp, athlon-mp"
Improved \s-1AMD\s0 Athlon \s-1CPU\s0 with \s-1MMX\s0, 3dNOW!, enhanced 3dNOW! and full \s-1SSE\s0
instruction set support.
.IP "\fIk8, opteron, athlon64, athlon-fx\fR" 4
.IX Item "k8, opteron, athlon64, athlon-fx"
\&\s-1AMD\s0 K8 core based CPUs with x86\-64 instruction set support.  (This supersets
\&\s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, 3dNOW!, enhanced 3dNOW! and 64\-bit instruction set extensions.)
.IP "\fIk8\-sse3, opteron\-sse3, athlon64\-sse3\fR" 4
.IX Item "k8-sse3, opteron-sse3, athlon64-sse3"
Improved versions of k8, opteron and athlon64 with \s-1SSE3\s0 instruction set support.
.IP "\fIamdfam10, barcelona\fR" 4
.IX Item "amdfam10, barcelona"
\&\s-1AMD\s0 Family 10h core based CPUs with x86\-64 instruction set support.  (This
supersets \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSE4A\s0, 3dNOW!, enhanced 3dNOW!, \s-1ABM\s0 and 64\-bit
instruction set extensions.)
.IP "\fIwinchip\-c6\fR" 4
.IX Item "winchip-c6"
\&\s-1IDT\s0 Winchip C6 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 instruction
set support.
.IP "\fIwinchip2\fR" 4
.IX Item "winchip2"
\&\s-1IDT\s0 Winchip2 \s-1CPU\s0, dealt in same way as i486 with additional \s-1MMX\s0 and 3dNOW!
instruction set support.
.IP "\fIc3\fR" 4
.IX Item "c3"
Via C3 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support.  (No scheduling is
implemented for this chip.)
.IP "\fIc3\-2\fR" 4
.IX Item "c3-2"
Via C3\-2 \s-1CPU\s0 with \s-1MMX\s0 and \s-1SSE\s0 instruction set support.  (No scheduling is
implemented for this chip.)
.IP "\fIgeode\fR" 4
.IX Item "geode"
Embedded \s-1AMD\s0 \s-1CPU\s0 with \s-1MMX\s0 and 3dNOW! instruction set support.
.RE
.RS 4
.Sp
While picking a specific \fIcpu-type\fR will schedule things appropriately
for that particular chip, the compiler will not generate any code that
does not run on the i386 without the \fB\-march=\fR\fIcpu-type\fR option
being used.
.RE
.IP "\fB\-march=\fR\fIcpu-type\fR" 4
.IX Item "-march=cpu-type"
Generate instructions for the machine type \fIcpu-type\fR.  The choices
for \fIcpu-type\fR are the same as for \fB\-mtune\fR.  Moreover,
specifying \fB\-march=\fR\fIcpu-type\fR implies \fB\-mtune=\fR\fIcpu-type\fR.
.IP "\fB\-mcpu=\fR\fIcpu-type\fR" 4
.IX Item "-mcpu=cpu-type"
A deprecated synonym for \fB\-mtune\fR.
.IP "\fB\-mfpmath=\fR\fIunit\fR" 4
.IX Item "-mfpmath=unit"
Generate floating point arithmetics for selected unit \fIunit\fR.  The choices
for \fIunit\fR are:
.RS 4
.IP "\fB387\fR" 4
.IX Item "387"
Use the standard 387 floating point coprocessor present majority of chips and
emulated otherwise.  Code compiled with this option will run almost everywhere.
The temporary results are computed in 80bit precision instead of precision
specified by the type resulting in slightly different results compared to most
of other chips.  See \fB\-ffloat\-store\fR for more detailed description.
.Sp
This is the default choice for i386 compiler.
.IP "\fBsse\fR" 4
.IX Item "sse"
Use scalar floating point instructions present in the \s-1SSE\s0 instruction set.
This instruction set is supported by Pentium3 and newer chips, in the \s-1AMD\s0 line
by Athlon\-4, Athlon-xp and Athlon-mp chips.  The earlier version of \s-1SSE\s0
instruction set supports only single precision arithmetics, thus the double and
extended precision arithmetics is still done using 387.  Later version, present
only in Pentium4 and the future \s-1AMD\s0 x86\-64 chips supports double precision
arithmetics too.
.Sp
For the i386 compiler, you need to use \fB\-march=\fR\fIcpu-type\fR, \fB\-msse\fR
or \fB\-msse2\fR switches to enable \s-1SSE\s0 extensions and make this option
effective.  For the x86\-64 compiler, these extensions are enabled by default.
.Sp
The resulting code should be considerably faster in the majority of cases and avoid
the numerical instability problems of 387 code, but may break some existing
code that expects temporaries to be 80bit.
.Sp
This is the default choice for the x86\-64 compiler.
.IP "\fBsse,387\fR" 4
.IX Item "sse,387"
Attempt to utilize both instruction sets at once.  This effectively double the
amount of available registers and on chips with separate execution units for
387 and \s-1SSE\s0 the execution resources too.  Use this option with care, as it is
still experimental, because the \s-1GCC\s0 register allocator does not model separate
functional units well resulting in instable performance.
.RE
.RS 4
.RE
.IP "\fB\-masm=\fR\fIdialect\fR" 4
.IX Item "-masm=dialect"
Output asm instructions using selected \fIdialect\fR.  Supported
choices are \fBintel\fR or \fBatt\fR (the default one).  Darwin does
not support \fBintel\fR.
.IP "\fB\-mieee\-fp\fR" 4
.IX Item "-mieee-fp"
.PD 0
.IP "\fB\-mno\-ieee\-fp\fR" 4
.IX Item "-mno-ieee-fp"
.PD
Control whether or not the compiler uses \s-1IEEE\s0 floating point
comparisons.  These handle correctly the case where the result of a
comparison is unordered.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not part of \s-1GCC\s0.
Normally the facilities of the machine's usual C compiler are used, but
this can't be done directly in cross-compilation.  You must make your
own arrangements to provide suitable library functions for
cross-compilation.
.Sp
On machines where a function returns floating point results in the 80387
register stack, some floating point opcodes may be emitted even if
\&\fB\-msoft\-float\fR is used.
.IP "\fB\-mno\-fp\-ret\-in\-387\fR" 4
.IX Item "-mno-fp-ret-in-387"
Do not use the \s-1FPU\s0 registers for return values of functions.
.Sp
The usual calling convention has functions return values of types
\&\f(CW\*(C`float\*(C'\fR and \f(CW\*(C`double\*(C'\fR in an \s-1FPU\s0 register, even if there
is no \s-1FPU\s0.  The idea is that the operating system should emulate
an \s-1FPU\s0.
.Sp
The option \fB\-mno\-fp\-ret\-in\-387\fR causes such values to be returned
in ordinary \s-1CPU\s0 registers instead.
.IP "\fB\-mno\-fancy\-math\-387\fR" 4
.IX Item "-mno-fancy-math-387"
Some 387 emulators do not support the \f(CW\*(C`sin\*(C'\fR, \f(CW\*(C`cos\*(C'\fR and
\&\f(CW\*(C`sqrt\*(C'\fR instructions for the 387.  Specify this option to avoid
generating those instructions.  This option is the default on FreeBSD,
OpenBSD and NetBSD.  This option is overridden when \fB\-march\fR
indicates that the target cpu will always have an \s-1FPU\s0 and so the
instruction will not need emulation.  As of revision 2.6.1, these
instructions are not generated unless you also use the
\&\fB\-funsafe\-math\-optimizations\fR switch.
.IP "\fB\-malign\-double\fR" 4
.IX Item "-malign-double"
.PD 0
.IP "\fB\-mno\-align\-double\fR" 4
.IX Item "-mno-align-double"
.PD
Control whether \s-1GCC\s0 aligns \f(CW\*(C`double\*(C'\fR, \f(CW\*(C`long double\*(C'\fR, and
\&\f(CW\*(C`long long\*(C'\fR variables on a two word boundary or a one word
boundary.  Aligning \f(CW\*(C`double\*(C'\fR variables on a two word boundary will
produce code that runs somewhat faster on a \fBPentium\fR at the
expense of more memory.
.Sp
On x86\-64, \fB\-malign\-double\fR is enabled by default.
.Sp
\&\fBWarning:\fR if you use the \fB\-malign\-double\fR switch,
structures containing the above types will be aligned differently than
the published application binary interface specifications for the 386
and will not be binary compatible with structures in code compiled
without that switch.
.IP "\fB\-m96bit\-long\-double\fR" 4
.IX Item "-m96bit-long-double"
.PD 0
.IP "\fB\-m128bit\-long\-double\fR" 4
.IX Item "-m128bit-long-double"
.PD
These switches control the size of \f(CW\*(C`long double\*(C'\fR type.  The i386
application binary interface specifies the size to be 96 bits,
so \fB\-m96bit\-long\-double\fR is the default in 32 bit mode.
.Sp
Modern architectures (Pentium and newer) would prefer \f(CW\*(C`long double\*(C'\fR
to be aligned to an 8 or 16 byte boundary.  In arrays or structures
conforming to the \s-1ABI\s0, this would not be possible.  So specifying a
\&\fB\-m128bit\-long\-double\fR will align \f(CW\*(C`long double\*(C'\fR
to a 16 byte boundary by padding the \f(CW\*(C`long double\*(C'\fR with an additional
32 bit zero.
.Sp
In the x86\-64 compiler, \fB\-m128bit\-long\-double\fR is the default choice as
its \s-1ABI\s0 specifies that \f(CW\*(C`long double\*(C'\fR is to be aligned on 16 byte boundary.
.Sp
Notice that neither of these options enable any extra precision over the x87
standard of 80 bits for a \f(CW\*(C`long double\*(C'\fR.
.Sp
\&\fBWarning:\fR if you override the default value for your target \s-1ABI\s0, the
structures and arrays containing \f(CW\*(C`long double\*(C'\fR variables will change
their size as well as function calling convention for function taking
\&\f(CW\*(C`long double\*(C'\fR will be modified.  Hence they will not be binary
compatible with arrays or structures in code compiled without that switch.
.IP "\fB\-mmlarge\-data\-threshold=\fR\fInumber\fR" 4
.IX Item "-mmlarge-data-threshold=number"
When \fB\-mcmodel=medium\fR is specified, the data greater than
\&\fIthreshold\fR are placed in large data section.  This value must be the
same across all object linked into the binary and defaults to 65535.
.IP "\fB\-mrtd\fR" 4
.IX Item "-mrtd"
Use a different function-calling convention, in which functions that
take a fixed number of arguments return with the \f(CW\*(C`ret\*(C'\fR \fInum\fR
instruction, which pops their arguments while returning.  This saves one
instruction in the caller since there is no need to pop the arguments
there.
.Sp
You can specify that an individual function is called with this calling
sequence with the function attribute \fBstdcall\fR.  You can also
override the \fB\-mrtd\fR option by using the function attribute
\&\fBcdecl\fR.
.Sp
\&\fBWarning:\fR this calling convention is incompatible with the one
normally used on Unix, so you cannot use it if you need to call
libraries compiled with the Unix compiler.
.Sp
Also, you must provide function prototypes for all functions that
take variable numbers of arguments (including \f(CW\*(C`printf\*(C'\fR);
otherwise incorrect code will be generated for calls to those
functions.
.Sp
In addition, seriously incorrect code will result if you call a
function with too many arguments.  (Normally, extra arguments are
harmlessly ignored.)
.IP "\fB\-mregparm=\fR\fInum\fR" 4
.IX Item "-mregparm=num"
Control how many registers are used to pass integer arguments.  By
default, no registers are used to pass arguments, and at most 3
registers can be used.  You can control this behavior for a specific
function by using the function attribute \fBregparm\fR.
.Sp
\&\fBWarning:\fR if you use this switch, and
\&\fInum\fR is nonzero, then you must build all modules with the same
value, including any libraries.  This includes the system libraries and
startup modules.
.IP "\fB\-msseregparm\fR" 4
.IX Item "-msseregparm"
Use \s-1SSE\s0 register passing conventions for float and double arguments
and return values.  You can control this behavior for a specific
function by using the function attribute \fBsseregparm\fR.
.Sp
\&\fBWarning:\fR if you use this switch then you must build all
modules with the same value, including any libraries.  This includes
the system libraries and startup modules.
.IP "\fB\-mpc32\fR" 4
.IX Item "-mpc32"
.PD 0
.IP "\fB\-mpc64\fR" 4
.IX Item "-mpc64"
.IP "\fB\-mpc80\fR" 4
.IX Item "-mpc80"
.PD
Set 80387 floating-point precision to 32, 64 or 80 bits.  When \fB\-mpc32\fR
is specified, the significands of results of floating-point operations are
rounded to 24 bits (single precision); \fB\-mpc64\fR rounds the the
significands of results of floating-point operations to 53 bits (double
precision) and \fB\-mpc80\fR rounds the significands of results of
floating-point operations to 64 bits (extended double precision), which is
the default.  When this option is used, floating-point operations in higher
precisions are not available to the programmer without setting the \s-1FPU\s0
control word explicitly.
.Sp
Setting the rounding of floating-point operations to less than the default
80 bits can speed some programs by 2% or more.  Note that some mathematical
libraries assume that extended precision (80 bit) floating-point operations
are enabled by default; routines in such libraries could suffer significant
loss of accuracy, typically through so-called \*(L"catastrophic cancellation\*(R",
when this option is used to set the precision to less than extended precision.
.IP "\fB\-mstackrealign\fR" 4
.IX Item "-mstackrealign"
Realign the stack at entry.  On the Intel x86, the
\&\fB\-mstackrealign\fR option will generate an alternate prologue and
epilogue that realigns the runtime stack.  This supports mixing legacy
codes that keep a 4\-byte aligned stack with modern codes that keep a
16\-byte stack for \s-1SSE\s0 compatibility.  The alternate prologue and
epilogue are slower and bigger than the regular ones, and the
alternate prologue requires an extra scratch register; this lowers the
number of registers available if used in conjunction with the
\&\f(CW\*(C`regparm\*(C'\fR attribute.  The \fB\-mstackrealign\fR option is
incompatible with the nested function prologue; this is considered a
hard error.  See also the attribute \f(CW\*(C`force_align_arg_pointer\*(C'\fR,
applicable to individual functions.
.IP "\fB\-mpreferred\-stack\-boundary=\fR\fInum\fR" 4
.IX Item "-mpreferred-stack-boundary=num"
Attempt to keep the stack boundary aligned to a 2 raised to \fInum\fR
byte boundary.  If \fB\-mpreferred\-stack\-boundary\fR is not specified,
the default is 4 (16 bytes or 128 bits).
.Sp
On Pentium and PentiumPro, \f(CW\*(C`double\*(C'\fR and \f(CW\*(C`long double\*(C'\fR values
should be aligned to an 8 byte boundary (see \fB\-malign\-double\fR) or
suffer significant run time performance penalties.  On Pentium \s-1III\s0, the
Streaming \s-1SIMD\s0 Extension (\s-1SSE\s0) data type \f(CW\*(C`_\|_m128\*(C'\fR may not work
properly if it is not 16 byte aligned.
.Sp
To ensure proper alignment of this values on the stack, the stack boundary
must be as aligned as that required by any value stored on the stack.
Further, every function must be generated such that it keeps the stack
aligned.  Thus calling a function compiled with a higher preferred
stack boundary from a function compiled with a lower preferred stack
boundary will most likely misalign the stack.  It is recommended that
libraries that use callbacks always use the default setting.
.Sp
This extra alignment does consume extra stack space, and generally
increases code size.  Code that is sensitive to stack space usage, such
as embedded systems and operating system kernels, may want to reduce the
preferred alignment to \fB\-mpreferred\-stack\-boundary=2\fR.
.IP "\fB\-mmmx\fR" 4
.IX Item "-mmmx"
.PD 0
.IP "\fB\-mno\-mmx\fR" 4
.IX Item "-mno-mmx"
.IP "\fB\-msse\fR" 4
.IX Item "-msse"
.IP "\fB\-mno\-sse\fR" 4
.IX Item "-mno-sse"
.IP "\fB\-msse2\fR" 4
.IX Item "-msse2"
.IP "\fB\-mno\-sse2\fR" 4
.IX Item "-mno-sse2"
.IP "\fB\-msse3\fR" 4
.IX Item "-msse3"
.IP "\fB\-mno\-sse3\fR" 4
.IX Item "-mno-sse3"
.IP "\fB\-mssse3\fR" 4
.IX Item "-mssse3"
.IP "\fB\-mno\-ssse3\fR" 4
.IX Item "-mno-ssse3"
.IP "\fB\-msse4.1\fR" 4
.IX Item "-msse4.1"
.IP "\fB\-mno\-sse4.1\fR" 4
.IX Item "-mno-sse4.1"
.IP "\fB\-msse4.2\fR" 4
.IX Item "-msse4.2"
.IP "\fB\-mno\-sse4.2\fR" 4
.IX Item "-mno-sse4.2"
.IP "\fB\-msse4\fR" 4
.IX Item "-msse4"
.IP "\fB\-mno\-sse4\fR" 4
.IX Item "-mno-sse4"
.IP "\fB\-msse4a\fR" 4
.IX Item "-msse4a"
.IP "\fB\-mno\-sse4a\fR" 4
.IX Item "-mno-sse4a"
.IP "\fB\-msse5\fR" 4
.IX Item "-msse5"
.IP "\fB\-mno\-sse5\fR" 4
.IX Item "-mno-sse5"
.IP "\fB\-m3dnow\fR" 4
.IX Item "-m3dnow"
.IP "\fB\-mno\-3dnow\fR" 4
.IX Item "-mno-3dnow"
.IP "\fB\-mpopcnt\fR" 4
.IX Item "-mpopcnt"
.IP "\fB\-mno\-popcnt\fR" 4
.IX Item "-mno-popcnt"
.IP "\fB\-mabm\fR" 4
.IX Item "-mabm"
.IP "\fB\-mno\-abm\fR" 4
.IX Item "-mno-abm"
.PD
These switches enable or disable the use of instructions in the \s-1MMX\s0,
\&\s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \s-1SSE4\s0.1, \s-1SSE4A\s0, \s-1SSE5\s0, \s-1ABM\s0 or 3DNow! extended
instruction sets.
These extensions are also available as built-in functions: see
\&\fBX86 Built-in Functions\fR, for details of the functions enabled and
disabled by these switches.
.Sp
To have \s-1SSE/SSE2\s0 instructions generated automatically from floating-point
code (as opposed to 387 instructions), see \fB\-mfpmath=sse\fR.
.Sp
These options will enable \s-1GCC\s0 to use these extended instructions in
generated code, even without \fB\-mfpmath=sse\fR.  Applications which
perform runtime \s-1CPU\s0 detection must compile separate files for each
supported architecture, using the appropriate flags.  In particular,
the file containing the \s-1CPU\s0 detection code should be compiled without
these options.
.IP "\fB\-mcld\fR" 4
.IX Item "-mcld"
This option instructs \s-1GCC\s0 to emit a \f(CW\*(C`cld\*(C'\fR instruction in the prologue
of functions that use string instructions.  String instructions depend on
the \s-1DF\s0 flag to select between autoincrement or autodecrement mode.  While the
\&\s-1ABI\s0 specifies the \s-1DF\s0 flag to be cleared on function entry, some operating
systems violate this specification by not clearing the \s-1DF\s0 flag in their
exception dispatchers.  The exception handler can be invoked with the \s-1DF\s0 flag
set which leads to wrong direction mode, when string instructions are used.
This option can be enabled by default on 32\-bit x86 targets by configuring
\&\s-1GCC\s0 with the \fB\-\-enable\-cld\fR configure option.  Generation of \f(CW\*(C`cld\*(C'\fR
instructions can be suppressed with the \fB\-mno\-cld\fR compiler option
in this case.
.IP "\fB\-mcx16\fR" 4
.IX Item "-mcx16"
This option will enable \s-1GCC\s0 to use \s-1CMPXCHG16B\s0 instruction in generated code.
\&\s-1CMPXCHG16B\s0 allows for atomic operations on 128\-bit double quadword (or oword)
data types.  This is useful for high resolution counters that could be updated
by multiple processors (or cores).  This instruction is generated as part of
atomic built-in functions: see \fBAtomic Builtins\fR for details.
.IP "\fB\-msahf\fR" 4
.IX Item "-msahf"
This option will enable \s-1GCC\s0 to use \s-1SAHF\s0 instruction in generated 64\-bit code.
Early Intel CPUs with Intel 64 lacked \s-1LAHF\s0 and \s-1SAHF\s0 instructions supported
by \s-1AMD64\s0 until introduction of Pentium 4 G1 step in December 2005.  \s-1LAHF\s0 and
\&\s-1SAHF\s0 are load and store instructions, respectively, for certain status flags.
In 64\-bit mode, \s-1SAHF\s0 instruction is used to optimize \f(CW\*(C`fmod\*(C'\fR, \f(CW\*(C`drem\*(C'\fR
or \f(CW\*(C`remainder\*(C'\fR built-in functions: see \fBOther Builtins\fR for details.
.IP "\fB\-mrecip\fR" 4
.IX Item "-mrecip"
This option will enable \s-1GCC\s0 to use \s-1RCPSS\s0 and \s-1RSQRTSS\s0 instructions (and their
vectorized variants \s-1RCPPS\s0 and \s-1RSQRTPS\s0) with an additional Newton-Rhapson step
to increase precision instead of \s-1DIVSS\s0 and \s-1SQRTSS\s0 (and their vectorized
variants) for single precision floating point arguments.  These instructions
are generated only when \fB\-funsafe\-math\-optimizations\fR is enabled
together with \fB\-finite\-math\-only\fR and \fB\-fno\-trapping\-math\fR.
Note that while the throughput of the sequence is higher than the throughput
of the non-reciprocal instruction, the precision of the sequence can be
decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
.IP "\fB\-mveclibabi=\fR\fItype\fR" 4
.IX Item "-mveclibabi=type"
Specifies the \s-1ABI\s0 type to use for vectorizing intrinsics using an
external library.  Supported types are \f(CW\*(C`acml\*(C'\fR for the \s-1AMD\s0
math core library style of interfacing.  \s-1GCC\s0 will currently emit
calls to \f(CW\*(C`_\|_vrd2_sin\*(C'\fR, \f(CW\*(C`_\|_vrd2_cos\*(C'\fR, \f(CW\*(C`_\|_vrd2_exp\*(C'\fR,
\&\f(CW\*(C`_\|_vrd2_log\*(C'\fR, \f(CW\*(C`_\|_vrd2_log2\*(C'\fR, \f(CW\*(C`_\|_vrd2_log10\*(C'\fR,
\&\f(CW\*(C`_\|_vrs4_sinf\*(C'\fR, \f(CW\*(C`_\|_vrs4_cosf\*(C'\fR, \f(CW\*(C`_\|_vrs4_expf\*(C'\fR,
\&\f(CW\*(C`_\|_vrs4_logf\*(C'\fR, \f(CW\*(C`_\|_vrs4_log2f\*(C'\fR, \f(CW\*(C`_\|_vrs4_log10f\*(C'\fR
and \f(CW\*(C`_\|_vrs4_powf\*(C'\fR when using this type and \fB\-ftree\-vectorize\fR
is enabled.  A \s-1ACML\s0 \s-1ABI\s0 compatible library will have to be specified
at link time.
.IP "\fB\-mpush\-args\fR" 4
.IX Item "-mpush-args"
.PD 0
.IP "\fB\-mno\-push\-args\fR" 4
.IX Item "-mno-push-args"
.PD
Use \s-1PUSH\s0 operations to store outgoing parameters.  This method is shorter
and usually equally fast as method using \s-1SUB/MOV\s0 operations and is enabled
by default.  In some cases disabling it may improve performance because of
improved scheduling and reduced dependencies.
.IP "\fB\-maccumulate\-outgoing\-args\fR" 4
.IX Item "-maccumulate-outgoing-args"
If enabled, the maximum amount of space required for outgoing arguments will be
computed in the function prologue.  This is faster on most modern CPUs
because of reduced dependencies, improved scheduling and reduced stack usage
when preferred stack boundary is not equal to 2.  The drawback is a notable
increase in code size.  This switch implies \fB\-mno\-push\-args\fR.
.IP "\fB\-mthreads\fR" 4
.IX Item "-mthreads"
Support thread-safe exception handling on \fBMingw32\fR.  Code that relies
on thread-safe exception handling must compile and link all code with the
\&\fB\-mthreads\fR option.  When compiling, \fB\-mthreads\fR defines
\&\fB\-D_MT\fR; when linking, it links in a special thread helper library
\&\fB\-lmingwthrd\fR which cleans up per thread exception handling data.
.IP "\fB\-mno\-align\-stringops\fR" 4
.IX Item "-mno-align-stringops"
Do not align destination of inlined string operations.  This switch reduces
code size and improves performance in case the destination is already aligned,
but \s-1GCC\s0 doesn't know about it.
.IP "\fB\-minline\-all\-stringops\fR" 4
.IX Item "-minline-all-stringops"
By default \s-1GCC\s0 inlines string operations only when destination is known to be
aligned at least to 4 byte boundary.  This enables more inlining, increase code
size, but may improve performance of code that depends on fast memcpy, strlen
and memset for short lengths.
.IP "\fB\-minline\-stringops\-dynamically\fR" 4
.IX Item "-minline-stringops-dynamically"
For string operation of unknown size, inline runtime checks so for small
blocks inline code is used, while for large blocks library call is used.
.IP "\fB\-mstringop\-strategy=\fR\fIalg\fR" 4
.IX Item "-mstringop-strategy=alg"
Overwrite internal decision heuristic about particular algorithm to inline
string operation with.  The allowed values are \f(CW\*(C`rep_byte\*(C'\fR,
\&\f(CW\*(C`rep_4byte\*(C'\fR, \f(CW\*(C`rep_8byte\*(C'\fR for expanding using i386 \f(CW\*(C`rep\*(C'\fR prefix
of sp