C'\fR variables on a 32\-bit
boundary (\fB\-malign\-int\fR) or a 16\-bit boundary (\fB\-mno\-align\-int\fR).
Aligning variables on 32\-bit boundaries produces code that runs somewhat
faster on processors with 32\-bit busses at the expense of more memory.
.Sp
\&\fBWarning:\fR if you use the \fB\-malign\-int\fR switch, \s-1GCC\s0 will
align structures containing the above types  differently than
most published application binary interface specifications for the m68k.
.IP "\fB\-mpcrel\fR" 4
.IX Item "-mpcrel"
Use the pc-relative addressing mode of the 68000 directly, instead of
using a global offset table.  At present, this option implies \fB\-fpic\fR,
allowing at most a 16\-bit offset for pc-relative addressing.  \fB\-fPIC\fR is
not presently supported with \fB\-mpcrel\fR, though this could be supported for
68020 and higher processors.
.IP "\fB\-mno\-strict\-align\fR" 4
.IX Item "-mno-strict-align"
.PD 0
.IP "\fB\-mstrict\-align\fR" 4
.IX Item "-mstrict-align"
.PD
Do not (do) assume that unaligned memory references will be handled by
the system.
.IP "\fB\-msep\-data\fR" 4
.IX Item "-msep-data"
Generate code that allows the data segment to be located in a different
area of memory from the text segment.  This allows for execute in place in
an environment without virtual memory management.  This option implies
\&\fB\-fPIC\fR.
.IP "\fB\-mno\-sep\-data\fR" 4
.IX Item "-mno-sep-data"
Generate code that assumes that the data segment follows the text segment.
This is the default.
.IP "\fB\-mid\-shared\-library\fR" 4
.IX Item "-mid-shared-library"
Generate code that supports shared libraries via the library \s-1ID\s0 method.
This allows for execute in place and shared libraries in an environment
without virtual memory management.  This option implies \fB\-fPIC\fR.
.IP "\fB\-mno\-id\-shared\-library\fR" 4
.IX Item "-mno-id-shared-library"
Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
This is the default.
.IP "\fB\-mshared\-library\-id=n\fR" 4
.IX Item "-mshared-library-id=n"
Specified the identification number of the \s-1ID\s0 based shared library being
compiled.  Specifying a value of 0 will generate more compact code, specifying
other values will force the allocation of that number to the current
library but is no more space or time efficient than omitting this option.
.PP
\fIM68hc1x Options\fR
.IX Subsection "M68hc1x Options"
.PP
These are the \fB\-m\fR options defined for the 68hc11 and 68hc12
microcontrollers.  The default values for these options depends on
which style of microcontroller was selected when the compiler was configured;
the defaults for the most common choices are given below.
.IP "\fB\-m6811\fR" 4
.IX Item "-m6811"
.PD 0
.IP "\fB\-m68hc11\fR" 4
.IX Item "-m68hc11"
.PD
Generate output for a 68HC11.  This is the default
when the compiler is configured for 68HC11\-based systems.
.IP "\fB\-m6812\fR" 4
.IX Item "-m6812"
.PD 0
.IP "\fB\-m68hc12\fR" 4
.IX Item "-m68hc12"
.PD
Generate output for a 68HC12.  This is the default
when the compiler is configured for 68HC12\-based systems.
.IP "\fB\-m68S12\fR" 4
.IX Item "-m68S12"
.PD 0
.IP "\fB\-m68hcs12\fR" 4
.IX Item "-m68hcs12"
.PD
Generate output for a 68HCS12.
.IP "\fB\-mauto\-incdec\fR" 4
.IX Item "-mauto-incdec"
Enable the use of 68HC12 pre and post auto-increment and auto-decrement
addressing modes.
.IP "\fB\-minmax\fR" 4
.IX Item "-minmax"
.PD 0
.IP "\fB\-nominmax\fR" 4
.IX Item "-nominmax"
.PD
Enable the use of 68HC12 min and max instructions.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.IP "\fB\-mno\-long\-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Treat all calls as being far away (near).  If calls are assumed to be
far away, the compiler will use the \f(CW\*(C`call\*(C'\fR instruction to
call a function and the \f(CW\*(C`rtc\*(C'\fR instruction for returning.
.IP "\fB\-mshort\fR" 4
.IX Item "-mshort"
Consider type \f(CW\*(C`int\*(C'\fR to be 16 bits wide, like \f(CW\*(C`short int\*(C'\fR.
.IP "\fB\-msoft\-reg\-count=\fR\fIcount\fR" 4
.IX Item "-msoft-reg-count=count"
Specify the number of pseudo-soft registers which are used for the
code generation.  The maximum number is 32.  Using more pseudo-soft
register may or may not result in better code depending on the program.
The default is 4 for 68HC11 and 2 for 68HC12.
.PP
\fIMCore Options\fR
.IX Subsection "MCore Options"
.PP
These are the \fB\-m\fR options defined for the Motorola M*Core
processors.
.IP "\fB\-mhardlit\fR" 4
.IX Item "-mhardlit"
.PD 0
.IP "\fB\-mno\-hardlit\fR" 4
.IX Item "-mno-hardlit"
.PD
Inline constants into the code stream if it can be done in two
instructions or less.
.IP "\fB\-mdiv\fR" 4
.IX Item "-mdiv"
.PD 0
.IP "\fB\-mno\-div\fR" 4
.IX Item "-mno-div"
.PD
Use the divide instruction.  (Enabled by default).
.IP "\fB\-mrelax\-immediate\fR" 4
.IX Item "-mrelax-immediate"
.PD 0
.IP "\fB\-mno\-relax\-immediate\fR" 4
.IX Item "-mno-relax-immediate"
.PD
Allow arbitrary sized immediates in bit operations.
.IP "\fB\-mwide\-bitfields\fR" 4
.IX Item "-mwide-bitfields"
.PD 0
.IP "\fB\-mno\-wide\-bitfields\fR" 4
.IX Item "-mno-wide-bitfields"
.PD
Always treat bit-fields as int-sized.
.IP "\fB\-m4byte\-functions\fR" 4
.IX Item "-m4byte-functions"
.PD 0
.IP "\fB\-mno\-4byte\-functions\fR" 4
.IX Item "-mno-4byte-functions"
.PD
Force all functions to be aligned to a four byte boundary.
.IP "\fB\-mcallgraph\-data\fR" 4
.IX Item "-mcallgraph-data"
.PD 0
.IP "\fB\-mno\-callgraph\-data\fR" 4
.IX Item "-mno-callgraph-data"
.PD
Emit callgraph information.
.IP "\fB\-mslow\-bytes\fR" 4
.IX Item "-mslow-bytes"
.PD 0
.IP "\fB\-mno\-slow\-bytes\fR" 4
.IX Item "-mno-slow-bytes"
.PD
Prefer word access when reading byte quantities.
.IP "\fB\-mlittle\-endian\fR" 4
.IX Item "-mlittle-endian"
.PD 0
.IP "\fB\-mbig\-endian\fR" 4
.IX Item "-mbig-endian"
.PD
Generate code for a little endian target.
.IP "\fB\-m210\fR" 4
.IX Item "-m210"
.PD 0
.IP "\fB\-m340\fR" 4
.IX Item "-m340"
.PD
Generate code for the 210 processor.
.PP
\fI\s-1MIPS\s0 Options\fR
.IX Subsection "MIPS Options"
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Generate big-endian code.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Generate little-endian code.  This is the default for \fBmips*el\-*\-*\fR
configurations.
.IP "\fB\-march=\fR\fIarch\fR" 4
.IX Item "-march=arch"
Generate code that will run on \fIarch\fR, which can be the name of a
generic \s-1MIPS\s0 \s-1ISA\s0, or the name of a particular processor.
The \s-1ISA\s0 names are:
\&\fBmips1\fR, \fBmips2\fR, \fBmips3\fR, \fBmips4\fR,
\&\fBmips32\fR, \fBmips32r2\fR, and \fBmips64\fR.
The processor names are:
\&\fB4kc\fR, \fB4km\fR, \fB4kp\fR, \fB4ksc\fR,
\&\fB4kec\fR, \fB4kem\fR, \fB4kep\fR, \fB4ksd\fR,
\&\fB5kc\fR, \fB5kf\fR,
\&\fB20kc\fR,
\&\fB24kc\fR, \fB24kf2_1\fR, \fB24kf1_1\fR,
\&\fB24kec\fR, \fB24kef2_1\fR, \fB24kef1_1\fR,
\&\fB34kc\fR, \fB34kf2_1\fR, \fB34kf1_1\fR,
\&\fB74kc\fR, \fB74kf2_1\fR, \fB74kf1_1\fR, \fB74kf3_2\fR,
\&\fBm4k\fR,
\&\fBorion\fR,
\&\fBr2000\fR, \fBr3000\fR, \fBr3900\fR, \fBr4000\fR, \fBr4400\fR,
\&\fBr4600\fR, \fBr4650\fR, \fBr6000\fR, \fBr8000\fR,
\&\fBrm7000\fR, \fBrm9000\fR,
\&\fBsb1\fR,
\&\fBsr71000\fR,
\&\fBvr4100\fR, \fBvr4111\fR, \fBvr4120\fR, \fBvr4130\fR, \fBvr4300\fR,
\&\fBvr5000\fR, \fBvr5400\fR and \fBvr5500\fR.
The special value \fBfrom-abi\fR selects the
most compatible architecture for the selected \s-1ABI\s0 (that is,
\&\fBmips1\fR for 32\-bit ABIs and \fBmips3\fR for 64\-bit ABIs).
.Sp
In processor names, a final \fB000\fR can be abbreviated as \fBk\fR
(for example, \fB\-march=r2k\fR).  Prefixes are optional, and
\&\fBvr\fR may be written \fBr\fR.
.Sp
Names of the form \fIn\fR\fBf2_1\fR refer to processors with
FPUs clocked at half the rate of the core, names of the form
\&\fIn\fR\fBf1_1\fR refer to processors with FPUs clocked at the same
rate as the core, and names of the form \fIn\fR\fBf3_2\fR refer to
processors with FPUs clocked a ratio of 3:2 with respect to the core.
For compatibility reasons, \fIn\fR\fBf\fR is accepted as a synonym
for \fIn\fR\fBf2_1\fR while \fIn\fR\fBx\fR and \fIb\fR\fBfx\fR are
accepted as synonyms for \fIn\fR\fBf1_1\fR.
.Sp
\&\s-1GCC\s0 defines two macros based on the value of this option.  The first
is \fB_MIPS_ARCH\fR, which gives the name of target architecture, as
a string.  The second has the form \fB_MIPS_ARCH_\fR\fIfoo\fR,
where \fIfoo\fR is the capitalized value of \fB_MIPS_ARCH\fR.
For example, \fB\-march=r2000\fR will set \fB_MIPS_ARCH\fR
to \fB\*(L"r2000\*(R"\fR and define the macro \fB_MIPS_ARCH_R2000\fR.
.Sp
Note that the \fB_MIPS_ARCH\fR macro uses the processor names given
above.  In other words, it will have the full prefix and will not
abbreviate \fB000\fR as \fBk\fR.  In the case of \fBfrom-abi\fR,
the macro names the resolved architecture (either \fB\*(L"mips1\*(R"\fR or
\&\fB\*(L"mips3\*(R"\fR).  It names the default architecture when no
\&\fB\-march\fR option is given.
.IP "\fB\-mtune=\fR\fIarch\fR" 4
.IX Item "-mtune=arch"
Optimize for \fIarch\fR.  Among other things, this option controls
the way instructions are scheduled, and the perceived cost of arithmetic
operations.  The list of \fIarch\fR values is the same as for
\&\fB\-march\fR.
.Sp
When this option is not used, \s-1GCC\s0 will optimize for the processor
specified by \fB\-march\fR.  By using \fB\-march\fR and
\&\fB\-mtune\fR together, it is possible to generate code that will
run on a family of processors, but optimize the code for one
particular member of that family.
.Sp
\&\fB\-mtune\fR defines the macros \fB_MIPS_TUNE\fR and
\&\fB_MIPS_TUNE_\fR\fIfoo\fR, which work in the same way as the
\&\fB\-march\fR ones described above.
.IP "\fB\-mips1\fR" 4
.IX Item "-mips1"
Equivalent to \fB\-march=mips1\fR.
.IP "\fB\-mips2\fR" 4
.IX Item "-mips2"
Equivalent to \fB\-march=mips2\fR.
.IP "\fB\-mips3\fR" 4
.IX Item "-mips3"
Equivalent to \fB\-march=mips3\fR.
.IP "\fB\-mips4\fR" 4
.IX Item "-mips4"
Equivalent to \fB\-march=mips4\fR.
.IP "\fB\-mips32\fR" 4
.IX Item "-mips32"
Equivalent to \fB\-march=mips32\fR.
.IP "\fB\-mips32r2\fR" 4
.IX Item "-mips32r2"
Equivalent to \fB\-march=mips32r2\fR.
.IP "\fB\-mips64\fR" 4
.IX Item "-mips64"
Equivalent to \fB\-march=mips64\fR.
.IP "\fB\-mips16\fR" 4
.IX Item "-mips16"
.PD 0
.IP "\fB\-mno\-mips16\fR" 4
.IX Item "-mno-mips16"
.PD
Generate (do not generate) \s-1MIPS16\s0 code.  If \s-1GCC\s0 is targetting a
\&\s-1MIPS32\s0 or \s-1MIPS64\s0 architecture, it will make use of the MIPS16e \s-1ASE\s0.
.Sp
\&\s-1MIPS16\s0 code generation can also be controlled on a per-function basis
by means of \f(CW\*(C`mips16\*(C'\fR and \f(CW\*(C`nomips16\*(C'\fR attributes.
.IP "\fB\-mflip\-mips16\fR" 4
.IX Item "-mflip-mips16"
Generate \s-1MIPS16\s0 code on alternating functions.  This option is provided
for regression testing of mixed MIPS16/non\-MIPS16 code generation, and is
not intended for ordinary use in compiling user code.
.IP "\fB\-minterlink\-mips16\fR" 4
.IX Item "-minterlink-mips16"
.PD 0
.IP "\fB\-mno\-interlink\-mips16\fR" 4
.IX Item "-mno-interlink-mips16"
.PD
Require (do not require) that non\-MIPS16 code be link-compatible with
\&\s-1MIPS16\s0 code.
.Sp
For example, non\-MIPS16 code cannot jump directly to \s-1MIPS16\s0 code;
it must either use a call or an indirect jump.  \fB\-minterlink\-mips16\fR
therefore disables direct jumps unless \s-1GCC\s0 knows that the target of the
jump is not \s-1MIPS16\s0.
.IP "\fB\-mabi=32\fR" 4
.IX Item "-mabi=32"
.PD 0
.IP "\fB\-mabi=o64\fR" 4
.IX Item "-mabi=o64"
.IP "\fB\-mabi=n32\fR" 4
.IX Item "-mabi=n32"
.IP "\fB\-mabi=64\fR" 4
.IX Item "-mabi=64"
.IP "\fB\-mabi=eabi\fR" 4
.IX Item "-mabi=eabi"
.PD
Generate code for the given \s-1ABI\s0.
.Sp
Note that the \s-1EABI\s0 has a 32\-bit and a 64\-bit variant.  \s-1GCC\s0 normally
generates 64\-bit code when you select a 64\-bit architecture, but you
can use \fB\-mgp32\fR to get 32\-bit code instead.
.Sp
For information about the O64 \s-1ABI\s0, see
<\fBhttp://gcc.gnu.org/projects/mipso64\-abi.html\fR>.
.Sp
\&\s-1GCC\s0 supports a variant of the o32 \s-1ABI\s0 in which floating-point registers
are 64 rather than 32 bits wide.  You can select this combination with
\&\fB\-mabi=32\fR \fB\-mfp64\fR.  This \s-1ABI\s0 relies on the \fBmthc1\fR
and \fBmfhc1\fR instructions and is therefore only supported for
\&\s-1MIPS32R2\s0 processors.
.Sp
The register assignments for arguments and return values remain the
same, but each scalar value is passed in a single 64\-bit register
rather than a pair of 32\-bit registers.  For example, scalar
floating-point values are returned in \fB\f(CB$f0\fB\fR only, not a
\&\fB\f(CB$f0\fB\fR/\fB\f(CB$f1\fB\fR pair.  The set of call-saved registers also
remains the same, but all 64 bits are saved.
.IP "\fB\-mabicalls\fR" 4
.IX Item "-mabicalls"
.PD 0
.IP "\fB\-mno\-abicalls\fR" 4
.IX Item "-mno-abicalls"
.PD
Generate (do not generate) code that is suitable for SVR4\-style
dynamic objects.  \fB\-mabicalls\fR is the default for SVR4\-based
systems.
.IP "\fB\-mshared\fR" 4
.IX Item "-mshared"
.PD 0
.IP "\fB\-mno\-shared\fR" 4
.IX Item "-mno-shared"
.PD
Generate (do not generate) code that is fully position-independent,
and that can therefore be linked into shared libraries.  This option
only affects \fB\-mabicalls\fR.
.Sp
All \fB\-mabicalls\fR code has traditionally been position-independent,
regardless of options like \fB\-fPIC\fR and \fB\-fpic\fR.  However,
as an extension, the \s-1GNU\s0 toolchain allows executables to use absolute
accesses for locally-binding symbols.  It can also use shorter \s-1GP\s0
initialization sequences and generate direct calls to locally-defined
functions.  This mode is selected by \fB\-mno\-shared\fR.
.Sp
\&\fB\-mno\-shared\fR depends on binutils 2.16 or higher and generates
objects that can only be linked by the \s-1GNU\s0 linker.  However, the option
does not affect the \s-1ABI\s0 of the final executable; it only affects the \s-1ABI\s0
of relocatable objects.  Using \fB\-mno\-shared\fR will generally make
executables both smaller and quicker.
.Sp
\&\fB\-mshared\fR is the default.
.IP "\fB\-mxgot\fR" 4
.IX Item "-mxgot"
.PD 0
.IP "\fB\-mno\-xgot\fR" 4
.IX Item "-mno-xgot"
.PD
Lift (do not lift) the usual restrictions on the size of the global
offset table.
.Sp
\&\s-1GCC\s0 normally uses a single instruction to load values from the \s-1GOT\s0.
While this is relatively efficient, it will only work if the \s-1GOT\s0
is smaller than about 64k.  Anything larger will cause the linker
to report an error such as:
.Sp
.Vb 1
\&        relocation truncated to fit: R_MIPS_GOT16 foobar
.Ve
.Sp
If this happens, you should recompile your code with \fB\-mxgot\fR.
It should then work with very large GOTs, although it will also be
less efficient, since it will take three instructions to fetch the
value of a global symbol.
.Sp
Note that some linkers can create multiple GOTs.  If you have such a
linker, you should only need to use \fB\-mxgot\fR when a single object
file accesses more than 64k's worth of \s-1GOT\s0 entries.  Very few do.
.Sp
These options have no effect unless \s-1GCC\s0 is generating position
independent code.
.IP "\fB\-mgp32\fR" 4
.IX Item "-mgp32"
Assume that general-purpose registers are 32 bits wide.
.IP "\fB\-mgp64\fR" 4
.IX Item "-mgp64"
Assume that general-purpose registers are 64 bits wide.
.IP "\fB\-mfp32\fR" 4
.IX Item "-mfp32"
Assume that floating-point registers are 32 bits wide.
.IP "\fB\-mfp64\fR" 4
.IX Item "-mfp64"
Assume that floating-point registers are 64 bits wide.
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
Use floating-point coprocessor instructions.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Do not use floating-point coprocessor instructions.  Implement
floating-point calculations using library calls instead.
.IP "\fB\-msingle\-float\fR" 4
.IX Item "-msingle-float"
Assume that the floating-point coprocessor only supports single-precision
operations.
.IP "\fB\-mdouble\-float\fR" 4
.IX Item "-mdouble-float"
Assume that the floating-point coprocessor supports double-precision
operations.  This is the default.
.IP "\fB\-mllsc\fR" 4
.IX Item "-mllsc"
.PD 0
.IP "\fB\-mno\-llsc\fR" 4
.IX Item "-mno-llsc"
.PD
Use (do not use) \fBll\fR, \fBsc\fR, and \fBsync\fR instructions to
implement atomic memory built-in functions.  When neither option is
specified, \s-1GCC\s0 will use the instructions if the target architecture
supports them.
.Sp
\&\fB\-mllsc\fR is useful if the runtime environment can emulate the
instructions and \fB\-mno\-llsc\fR can be useful when compiling for
nonstandard ISAs.  You can make either option the default by
configuring \s-1GCC\s0 with \fB\-\-with\-llsc\fR and \fB\-\-without\-llsc\fR
respectively.  \fB\-\-with\-llsc\fR is the default for some
configurations; see the installation documentation for details.
.IP "\fB\-mdsp\fR" 4
.IX Item "-mdsp"
.PD 0
.IP "\fB\-mno\-dsp\fR" 4
.IX Item "-mno-dsp"
.PD
Use (do not use) revision 1 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0.
  This option defines the
preprocessor macro \fB_\|_mips_dsp\fR.  It also defines
\&\fB_\|_mips_dsp_rev\fR to 1.
.IP "\fB\-mdspr2\fR" 4
.IX Item "-mdspr2"
.PD 0
.IP "\fB\-mno\-dspr2\fR" 4
.IX Item "-mno-dspr2"
.PD
Use (do not use) revision 2 of the \s-1MIPS\s0 \s-1DSP\s0 \s-1ASE\s0.
  This option defines the
preprocessor macros \fB_\|_mips_dsp\fR and \fB_\|_mips_dspr2\fR.
It also defines \fB_\|_mips_dsp_rev\fR to 2.
.IP "\fB\-msmartmips\fR" 4
.IX Item "-msmartmips"
.PD 0
.IP "\fB\-mno\-smartmips\fR" 4
.IX Item "-mno-smartmips"
.PD
Use (do not use) the \s-1MIPS\s0 SmartMIPS \s-1ASE\s0.
.IP "\fB\-mpaired\-single\fR" 4
.IX Item "-mpaired-single"
.PD 0
.IP "\fB\-mno\-paired\-single\fR" 4
.IX Item "-mno-paired-single"
.PD
Use (do not use) paired-single floating-point instructions.
  This option requires
hardware floating-point support to be enabled.
.IP "\fB\-mdmx\fR" 4
.IX Item "-mdmx"
.PD 0
.IP "\fB\-mno\-mdmx\fR" 4
.IX Item "-mno-mdmx"
.PD
Use (do not use) \s-1MIPS\s0 Digital Media Extension instructions.
This option can only be used when generating 64\-bit code and requires
hardware floating-point support to be enabled.
.IP "\fB\-mips3d\fR" 4
.IX Item "-mips3d"
.PD 0
.IP "\fB\-mno\-mips3d\fR" 4
.IX Item "-mno-mips3d"
.PD
Use (do not use) the \s-1MIPS\-3D\s0 \s-1ASE\s0.  
The option \fB\-mips3d\fR implies \fB\-mpaired\-single\fR.
.IP "\fB\-mmt\fR" 4
.IX Item "-mmt"
.PD 0
.IP "\fB\-mno\-mt\fR" 4
.IX Item "-mno-mt"
.PD
Use (do not use) \s-1MT\s0 Multithreading instructions.
.IP "\fB\-mlong64\fR" 4
.IX Item "-mlong64"
Force \f(CW\*(C`long\*(C'\fR types to be 64 bits wide.  See \fB\-mlong32\fR for
an explanation of the default and the way that the pointer size is
determined.
.IP "\fB\-mlong32\fR" 4
.IX Item "-mlong32"
Force \f(CW\*(C`long\*(C'\fR, \f(CW\*(C`int\*(C'\fR, and pointer types to be 32 bits wide.
.Sp
The default size of \f(CW\*(C`int\*(C'\fRs, \f(CW\*(C`long\*(C'\fRs and pointers depends on
the \s-1ABI\s0.  All the supported ABIs use 32\-bit \f(CW\*(C`int\*(C'\fRs.  The n64 \s-1ABI\s0
uses 64\-bit \f(CW\*(C`long\*(C'\fRs, as does the 64\-bit \s-1EABI\s0; the others use
32\-bit \f(CW\*(C`long\*(C'\fRs.  Pointers are the same size as \f(CW\*(C`long\*(C'\fRs,
or the same size as integer registers, whichever is smaller.
.IP "\fB\-msym32\fR" 4
.IX Item "-msym32"
.PD 0
.IP "\fB\-mno\-sym32\fR" 4
.IX Item "-mno-sym32"
.PD
Assume (do not assume) that all symbols have 32\-bit values, regardless
of the selected \s-1ABI\s0.  This option is useful in combination with
\&\fB\-mabi=64\fR and \fB\-mno\-abicalls\fR because it allows \s-1GCC\s0
to generate shorter and faster references to symbolic addresses.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
Put definitions of externally-visible data in a small data section
if that data is no bigger than \fInum\fR bytes.  \s-1GCC\s0 can then access
the data more efficiently; see \fB\-mgpopt\fR for details.
.Sp
The default \fB\-G\fR option depends on the configuration.
.IP "\fB\-mlocal\-sdata\fR" 4
.IX Item "-mlocal-sdata"
.PD 0
.IP "\fB\-mno\-local\-sdata\fR" 4
.IX Item "-mno-local-sdata"
.PD
Extend (do not extend) the \fB\-G\fR behavior to local data too,
such as to static variables in C.  \fB\-mlocal\-sdata\fR is the
default for all configurations.
.Sp
If the linker complains that an application is using too much small data,
you might want to try rebuilding the less performance-critical parts with
\&\fB\-mno\-local\-sdata\fR.  You might also want to build large
libraries with \fB\-mno\-local\-sdata\fR, so that the libraries leave
more room for the main program.
.IP "\fB\-mextern\-sdata\fR" 4
.IX Item "-mextern-sdata"
.PD 0
.IP "\fB\-mno\-extern\-sdata\fR" 4
.IX Item "-mno-extern-sdata"
.PD
Assume (do not assume) that externally-defined data will be in
a small data section if that data is within the \fB\-G\fR limit.
\&\fB\-mextern\-sdata\fR is the default for all configurations.
.Sp
If you compile a module \fIMod\fR with \fB\-mextern\-sdata\fR \fB\-G\fR
\&\fInum\fR \fB\-mgpopt\fR, and \fIMod\fR references a variable \fIVar\fR
that is no bigger than \fInum\fR bytes, you must make sure that \fIVar\fR
is placed in a small data section.  If \fIVar\fR is defined by another
module, you must either compile that module with a high-enough
\&\fB\-G\fR setting or attach a \f(CW\*(C`section\*(C'\fR attribute to \fIVar\fR's
definition.  If \fIVar\fR is common, you must link the application
with a high-enough \fB\-G\fR setting.
.Sp
The easiest way of satisfying these restrictions is to compile
and link every module with the same \fB\-G\fR option.  However,
you may wish to build a library that supports several different
small data limits.  You can do this by compiling the library with
the highest supported \fB\-G\fR setting and additionally using
\&\fB\-mno\-extern\-sdata\fR to stop the library from making assumptions
about externally-defined data.
.IP "\fB\-mgpopt\fR" 4
.IX Item "-mgpopt"
.PD 0
.IP "\fB\-mno\-gpopt\fR" 4
.IX Item "-mno-gpopt"
.PD
Use (do not use) GP-relative accesses for symbols that are known to be
in a small data section; see \fB\-G\fR, \fB\-mlocal\-sdata\fR and
\&\fB\-mextern\-sdata\fR.  \fB\-mgpopt\fR is the default for all
configurations.
.Sp
\&\fB\-mno\-gpopt\fR is useful for cases where the \f(CW$gp\fR register
might not hold the value of \f(CW\*(C`_gp\*(C'\fR.  For example, if the code is
part of a library that might be used in a boot monitor, programs that
call boot monitor routines will pass an unknown value in \f(CW$gp\fR.
(In such situations, the boot monitor itself would usually be compiled
with \fB\-G0\fR.)
.Sp
\&\fB\-mno\-gpopt\fR implies \fB\-mno\-local\-sdata\fR and
\&\fB\-mno\-extern\-sdata\fR.
.IP "\fB\-membedded\-data\fR" 4
.IX Item "-membedded-data"
.PD 0
.IP "\fB\-mno\-embedded\-data\fR" 4
.IX Item "-mno-embedded-data"
.PD
Allocate variables to the read-only data section first if possible, then
next in the small data section if possible, otherwise in data.  This gives
slightly slower code than the default, but reduces the amount of \s-1RAM\s0 required
when executing, and thus may be preferred for some embedded systems.
.IP "\fB\-muninit\-const\-in\-rodata\fR" 4
.IX Item "-muninit-const-in-rodata"
.PD 0
.IP "\fB\-mno\-uninit\-const\-in\-rodata\fR" 4
.IX Item "-mno-uninit-const-in-rodata"
.PD
Put uninitialized \f(CW\*(C`const\*(C'\fR variables in the read-only data section.
This option is only meaningful in conjunction with \fB\-membedded\-data\fR.
.IP "\fB\-mcode\-readable=\fR\fIsetting\fR" 4
.IX Item "-mcode-readable=setting"
Specify whether \s-1GCC\s0 may generate code that reads from executable sections.
There are three possible settings:
.RS 4
.IP "\fB\-mcode\-readable=yes\fR" 4
.IX Item "-mcode-readable=yes"
Instructions may freely access executable sections.  This is the
default setting.
.IP "\fB\-mcode\-readable=pcrel\fR" 4
.IX Item "-mcode-readable=pcrel"
\&\s-1MIPS16\s0 PC-relative load instructions can access executable sections,
but other instructions must not do so.  This option is useful on 4KSc
and 4KSd processors when the code TLBs have the Read Inhibit bit set.
It is also useful on processors that can be configured to have a dual
instruction/data \s-1SRAM\s0 interface and that, like the M4K, automatically
redirect PC-relative loads to the instruction \s-1RAM\s0.
.IP "\fB\-mcode\-readable=no\fR" 4
.IX Item "-mcode-readable=no"
Instructions must not access executable sections.  This option can be
useful on targets that are configured to have a dual instruction/data
\&\s-1SRAM\s0 interface but that (unlike the M4K) do not automatically redirect
PC-relative loads to the instruction \s-1RAM\s0.
.RE
.RS 4
.RE
.IP "\fB\-msplit\-addresses\fR" 4
.IX Item "-msplit-addresses"
.PD 0
.IP "\fB\-mno\-split\-addresses\fR" 4
.IX Item "-mno-split-addresses"
.PD
Enable (disable) use of the \f(CW\*(C`%hi()\*(C'\fR and \f(CW\*(C`%lo()\*(C'\fR assembler
relocation operators.  This option has been superseded by
\&\fB\-mexplicit\-relocs\fR but is retained for backwards compatibility.
.IP "\fB\-mexplicit\-relocs\fR" 4
.IX Item "-mexplicit-relocs"
.PD 0
.IP "\fB\-mno\-explicit\-relocs\fR" 4
.IX Item "-mno-explicit-relocs"
.PD
Use (do not use) assembler relocation operators when dealing with symbolic
addresses.  The alternative, selected by \fB\-mno\-explicit\-relocs\fR,
is to use assembler macros instead.
.Sp
\&\fB\-mexplicit\-relocs\fR is the default if \s-1GCC\s0 was configured
to use an assembler that supports relocation operators.
.IP "\fB\-mcheck\-zero\-division\fR" 4
.IX Item "-mcheck-zero-division"
.PD 0
.IP "\fB\-mno\-check\-zero\-division\fR" 4
.IX Item "-mno-check-zero-division"
.PD
Trap (do not trap) on integer division by zero.
.Sp
The default is \fB\-mcheck\-zero\-division\fR.
.IP "\fB\-mdivide\-traps\fR" 4
.IX Item "-mdivide-traps"
.PD 0
.IP "\fB\-mdivide\-breaks\fR" 4
.IX Item "-mdivide-breaks"
.PD
\&\s-1MIPS\s0 systems check for division by zero by generating either a
conditional trap or a break instruction.  Using traps results in
smaller code, but is only supported on \s-1MIPS\s0 \s-1II\s0 and later.  Also, some
versions of the Linux kernel have a bug that prevents trap from
generating the proper signal (\f(CW\*(C`SIGFPE\*(C'\fR).  Use \fB\-mdivide\-traps\fR to
allow conditional traps on architectures that support them and
\&\fB\-mdivide\-breaks\fR to force the use of breaks.
.Sp
The default is usually \fB\-mdivide\-traps\fR, but this can be
overridden at configure time using \fB\-\-with\-divide=breaks\fR.
Divide-by-zero checks can be completely disabled using
\&\fB\-mno\-check\-zero\-division\fR.
.IP "\fB\-mmemcpy\fR" 4
.IX Item "-mmemcpy"
.PD 0
.IP "\fB\-mno\-memcpy\fR" 4
.IX Item "-mno-memcpy"
.PD
Force (do not force) the use of \f(CW\*(C`memcpy()\*(C'\fR for non-trivial block
moves.  The default is \fB\-mno\-memcpy\fR, which allows \s-1GCC\s0 to inline
most constant-sized copies.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.IP "\fB\-mno\-long\-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Disable (do not disable) use of the \f(CW\*(C`jal\*(C'\fR instruction.  Calling
functions using \f(CW\*(C`jal\*(C'\fR is more efficient but requires the caller
and callee to be in the same 256 megabyte segment.
.Sp
This option has no effect on abicalls code.  The default is
\&\fB\-mno\-long\-calls\fR.
.IP "\fB\-mmad\fR" 4
.IX Item "-mmad"
.PD 0
.IP "\fB\-mno\-mad\fR" 4
.IX Item "-mno-mad"
.PD
Enable (disable) use of the \f(CW\*(C`mad\*(C'\fR, \f(CW\*(C`madu\*(C'\fR and \f(CW\*(C`mul\*(C'\fR
instructions, as provided by the R4650 \s-1ISA\s0.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mno\-fused\-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Enable (disable) use of the floating point multiply-accumulate
instructions, when they are available.  The default is
\&\fB\-mfused\-madd\fR.
.Sp
When multiply-accumulate instructions are used, the intermediate
product is calculated to infinite precision and is not subject to
the \s-1FCSR\s0 Flush to Zero bit.  This may be undesirable in some
circumstances.
.IP "\fB\-nocpp\fR" 4
.IX Item "-nocpp"
Tell the \s-1MIPS\s0 assembler to not run its preprocessor over user
assembler files (with a \fB.s\fR suffix) when assembling them.
.IP "\fB\-mfix\-r4000\fR" 4
.IX Item "-mfix-r4000"
.PD 0
.IP "\fB\-mno\-fix\-r4000\fR" 4
.IX Item "-mno-fix-r4000"
.PD
Work around certain R4000 \s-1CPU\s0 errata:
.RS 4
.IP "\-" 4
A double-word or a variable shift may give an incorrect result if executed
immediately after starting an integer division.
.IP "\-" 4
A double-word or a variable shift may give an incorrect result if executed
while an integer multiplication is in progress.
.IP "\-" 4
An integer division may give an incorrect result if started in a delay slot
of a taken branch or a jump.
.RE
.RS 4
.RE
.IP "\fB\-mfix\-r4400\fR" 4
.IX Item "-mfix-r4400"
.PD 0
.IP "\fB\-mno\-fix\-r4400\fR" 4
.IX Item "-mno-fix-r4400"
.PD
Work around certain R4400 \s-1CPU\s0 errata:
.RS 4
.IP "\-" 4
A double-word or a variable shift may give an incorrect result if executed
immediately after starting an integer division.
.RE
.RS 4
.RE
.IP "\fB\-mfix\-vr4120\fR" 4
.IX Item "-mfix-vr4120"
.PD 0
.IP "\fB\-mno\-fix\-vr4120\fR" 4
.IX Item "-mno-fix-vr4120"
.PD
Work around certain \s-1VR4120\s0 errata:
.RS 4
.IP "\-" 4
\&\f(CW\*(C`dmultu\*(C'\fR does not always produce the correct result.
.IP "\-" 4
\&\f(CW\*(C`div\*(C'\fR and \f(CW\*(C`ddiv\*(C'\fR do not always produce the correct result if one
of the operands is negative.
.RE
.RS 4
.Sp
The workarounds for the division errata rely on special functions in
\&\fIlibgcc.a\fR.  At present, these functions are only provided by
the \f(CW\*(C`mips64vr*\-elf\*(C'\fR configurations.
.Sp
Other \s-1VR4120\s0 errata require a nop to be inserted between certain pairs of
instructions.  These errata are handled by the assembler, not by \s-1GCC\s0 itself.
.RE
.IP "\fB\-mfix\-vr4130\fR" 4
.IX Item "-mfix-vr4130"
Work around the \s-1VR4130\s0 \f(CW\*(C`mflo\*(C'\fR/\f(CW\*(C`mfhi\*(C'\fR errata.  The
workarounds are implemented by the assembler rather than by \s-1GCC\s0,
although \s-1GCC\s0 will avoid using \f(CW\*(C`mflo\*(C'\fR and \f(CW\*(C`mfhi\*(C'\fR if the
\&\s-1VR4130\s0 \f(CW\*(C`macc\*(C'\fR, \f(CW\*(C`macchi\*(C'\fR, \f(CW\*(C`dmacc\*(C'\fR and \f(CW\*(C`dmacchi\*(C'\fR
instructions are available instead.
.IP "\fB\-mfix\-sb1\fR" 4
.IX Item "-mfix-sb1"
.PD 0
.IP "\fB\-mno\-fix\-sb1\fR" 4
.IX Item "-mno-fix-sb1"
.PD
Work around certain \s-1SB\-1\s0 \s-1CPU\s0 core errata.
(This flag currently works around the \s-1SB\-1\s0 revision 2
\&\*(L"F1\*(R" and \*(L"F2\*(R" floating point errata.)
.IP "\fB\-mflush\-func=\fR\fIfunc\fR" 4
.IX Item "-mflush-func=func"
.PD 0
.IP "\fB\-mno\-flush\-func\fR" 4
.IX Item "-mno-flush-func"
.PD
Specifies the function to call to flush the I and D caches, or to not
call any such function.  If called, the function must take the same
arguments as the common \f(CW\*(C`_flush_func()\*(C'\fR, that is, the address of the
memory range for which the cache is being flushed, the size of the
memory range, and the number 3 (to flush both caches).  The default
depends on the target \s-1GCC\s0 was configured for, but commonly is either
\&\fB_flush_func\fR or \fB_\|_cpu_flush\fR.
.IP "\fBmbranch\-cost=\fR\fInum\fR" 4
.IX Item "mbranch-cost=num"
Set the cost of branches to roughly \fInum\fR \*(L"simple\*(R" instructions.
This cost is only a heuristic and is not guaranteed to produce
consistent results across releases.  A zero cost redundantly selects
the default, which is based on the \fB\-mtune\fR setting.
.IP "\fB\-mbranch\-likely\fR" 4
.IX Item "-mbranch-likely"
.PD 0
.IP "\fB\-mno\-branch\-likely\fR" 4
.IX Item "-mno-branch-likely"
.PD
Enable or disable use of Branch Likely instructions, regardless of the
default for the selected architecture.  By default, Branch Likely
instructions may be generated if they are supported by the selected
architecture.  An exception is for the \s-1MIPS32\s0 and \s-1MIPS64\s0 architectures
and processors which implement those architectures; for those, Branch
Likely instructions will not be generated by default because the \s-1MIPS32\s0
and \s-1MIPS64\s0 architectures specifically deprecate their use.
.IP "\fB\-mfp\-exceptions\fR" 4
.IX Item "-mfp-exceptions"
.PD 0
.IP "\fB\-mno\-fp\-exceptions\fR" 4
.IX Item "-mno-fp-exceptions"
.PD
Specifies whether \s-1FP\s0 exceptions are enabled.  This affects how we schedule
\&\s-1FP\s0 instructions for some processors.  The default is that \s-1FP\s0 exceptions are
enabled.
.Sp
For instance, on the \s-1SB\-1\s0, if \s-1FP\s0 exceptions are disabled, and we are emitting
64\-bit code, then we can use both \s-1FP\s0 pipes.  Otherwise, we can only use one
\&\s-1FP\s0 pipe.
.IP "\fB\-mvr4130\-align\fR" 4
.IX Item "-mvr4130-align"
.PD 0
.IP "\fB\-mno\-vr4130\-align\fR" 4
.IX Item "-mno-vr4130-align"
.PD
The \s-1VR4130\s0 pipeline is two-way superscalar, but can only issue two
instructions together if the first one is 8\-byte aligned.  When this
option is enabled, \s-1GCC\s0 will align pairs of instructions that it
thinks should execute in parallel.
.Sp
This option only has an effect when optimizing for the \s-1VR4130\s0.
It normally makes code faster, but at the expense of making it bigger.
It is enabled by default at optimization level \fB\-O3\fR.
.PP
\fI\s-1MMIX\s0 Options\fR
.IX Subsection "MMIX Options"
.PP
These options are defined for the \s-1MMIX:\s0
.IP "\fB\-mlibfuncs\fR" 4
.IX Item "-mlibfuncs"
.PD 0
.IP "\fB\-mno\-libfuncs\fR" 4
.IX Item "-mno-libfuncs"
.PD
Specify that intrinsic library functions are being compiled, passing all
values in registers, no matter the size.
.IP "\fB\-mepsilon\fR" 4
.IX Item "-mepsilon"
.PD 0
.IP "\fB\-mno\-epsilon\fR" 4
.IX Item "-mno-epsilon"
.PD
Generate floating-point comparison instructions that compare with respect
to the \f(CW\*(C`rE\*(C'\fR epsilon register.
.IP "\fB\-mabi=mmixware\fR" 4
.IX Item "-mabi=mmixware"
.PD 0
.IP "\fB\-mabi=gnu\fR" 4
.IX Item "-mabi=gnu"
.PD
Generate code that passes function parameters and return values that (in
the called function) are seen as registers \f(CW$0\fR and up, as opposed to
the \s-1GNU\s0 \s-1ABI\s0 which uses global registers \f(CW$231\fR and up.
.IP "\fB\-mzero\-extend\fR" 4
.IX Item "-mzero-extend"
.PD 0
.IP "\fB\-mno\-zero\-extend\fR" 4
.IX Item "-mno-zero-extend"
.PD
When reading data from memory in sizes shorter than 64 bits, use (do not
use) zero-extending load instructions by default, rather than
sign-extending ones.
.IP "\fB\-mknuthdiv\fR" 4
.IX Item "-mknuthdiv"
.PD 0
.IP "\fB\-mno\-knuthdiv\fR" 4
.IX Item "-mno-knuthdiv"
.PD
Make the result of a division yielding a remainder have the same sign as
the divisor.  With the default, \fB\-mno\-knuthdiv\fR, the sign of the
remainder follows the sign of the dividend.  Both methods are
arithmetically valid, the latter being almost exclusively used.
.IP "\fB\-mtoplevel\-symbols\fR" 4
.IX Item "-mtoplevel-symbols"
.PD 0
.IP "\fB\-mno\-toplevel\-symbols\fR" 4
.IX Item "-mno-toplevel-symbols"
.PD
Prepend (do not prepend) a \fB:\fR to all global symbols, so the assembly
code can be used with the \f(CW\*(C`PREFIX\*(C'\fR assembly directive.
.IP "\fB\-melf\fR" 4
.IX Item "-melf"
Generate an executable in the \s-1ELF\s0 format, rather than the default
\&\fBmmo\fR format used by the \fBmmix\fR simulator.
.IP "\fB\-mbranch\-predict\fR" 4
.IX Item "-mbranch-predict"
.PD 0
.IP "\fB\-mno\-branch\-predict\fR" 4
.IX Item "-mno-branch-predict"
.PD
Use (do not use) the probable-branch instructions, when static branch
prediction indicates a probable branch.
.IP "\fB\-mbase\-addresses\fR" 4
.IX Item "-mbase-addresses"
.PD 0
.IP "\fB\-mno\-base\-addresses\fR" 4
.IX Item "-mno-base-addresses"
.PD
Generate (do not generate) code that uses \fIbase addresses\fR.  Using a
base address automatically generates a request (handled by the assembler
and the linker) for a constant to be set up in a global register.  The
register is used for one or more base address requests within the range 0
to 255 from the value held in the register.  The generally leads to short
and fast code, but the number of different data items that can be
addressed is limited.  This means that a program that uses lots of static
data may require \fB\-mno\-base\-addresses\fR.
.IP "\fB\-msingle\-exit\fR" 4
.IX Item "-msingle-exit"
.PD 0
.IP "\fB\-mno\-single\-exit\fR" 4
.IX Item "-mno-single-exit"
.PD
Force (do not force) generated code to have a single exit point in each
function.
.PP
\fI\s-1MN10300\s0 Options\fR
.IX Subsection "MN10300 Options"
.PP
These \fB\-m\fR options are defined for Matsushita \s-1MN10300\s0 architectures:
.IP "\fB\-mmult\-bug\fR" 4
.IX Item "-mmult-bug"
Generate code to avoid bugs in the multiply instructions for the \s-1MN10300\s0
processors.  This is the default.
.IP "\fB\-mno\-mult\-bug\fR" 4
.IX Item "-mno-mult-bug"
Do not generate code to avoid bugs in the multiply instructions for the
\&\s-1MN10300\s0 processors.
.IP "\fB\-mam33\fR" 4
.IX Item "-mam33"
Generate code which uses features specific to the \s-1AM33\s0 processor.
.IP "\fB\-mno\-am33\fR" 4
.IX Item "-mno-am33"
Do not generate code which uses features specific to the \s-1AM33\s0 processor.  This
is the default.
.IP "\fB\-mreturn\-pointer\-on\-d0\fR" 4
.IX Item "-mreturn-pointer-on-d0"
When generating a function which returns a pointer, return the pointer
in both \f(CW\*(C`a0\*(C'\fR and \f(CW\*(C`d0\*(C'\fR.  Otherwise, the pointer is returned
only in a0, and attempts to call such functions without a prototype
would result in errors.  Note that this option is on by default; use
\&\fB\-mno\-return\-pointer\-on\-d0\fR to disable it.
.IP "\fB\-mno\-crt0\fR" 4
.IX Item "-mno-crt0"
Do not link in the C run-time initialization object file.
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Indicate to the linker that it should perform a relaxation optimization pass
to shorten branches, calls and absolute memory addresses.  This option only
has an effect when used on the command line for the final link step.
.Sp
This option makes symbolic debugging impossible.
.PP
\fI\s-1MT\s0 Options\fR
.IX Subsection "MT Options"
.PP
These \fB\-m\fR options are defined for Morpho \s-1MT\s0 architectures:
.IP "\fB\-march=\fR\fIcpu-type\fR" 4
.IX Item "-march=cpu-type"
Generate code that will run on \fIcpu-type\fR, which is the name of a system
representing a certain processor type.  Possible values for
\&\fIcpu-type\fR are \fBms1\-64\-001\fR, \fBms1\-16\-002\fR,
\&\fBms1\-16\-003\fR and \fBms2\fR.
.Sp
When this option is not used, the default is \fB\-march=ms1\-16\-002\fR.
.IP "\fB\-mbacc\fR" 4
.IX Item "-mbacc"
Use byte loads and stores when generating code.
.IP "\fB\-mno\-bacc\fR" 4
.IX Item "-mno-bacc"
Do not use byte loads and stores when generating code.
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
Use simulator runtime
.IP "\fB\-mno\-crt0\fR" 4
.IX Item "-mno-crt0"
Do not link in the C run-time initialization object file
\&\fIcrti.o\fR.  Other run-time initialization and termination files
such as \fIstartup.o\fR and \fIexit.o\fR are still included on the
linker command line.
.PP
\fI\s-1PDP\-11\s0 Options\fR
.IX Subsection "PDP-11 Options"
.PP
These options are defined for the \s-1PDP\-11:\s0
.IP "\fB\-mfpu\fR" 4
.IX Item "-mfpu"
Use hardware \s-1FPP\s0 floating point.  This is the default.  (\s-1FIS\s0 floating
point on the \s-1PDP\-11/40\s0 is not supported.)
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Do not use hardware floating point.
.IP "\fB\-mac0\fR" 4
.IX Item "-mac0"
Return floating-point results in ac0 (fr0 in Unix assembler syntax).
.IP "\fB\-mno\-ac0\fR" 4
.IX Item "-mno-ac0"
Return floating-point results in memory.  This is the default.
.IP "\fB\-m40\fR" 4
.IX Item "-m40"
Generate code for a \s-1PDP\-11/40\s0.
.IP "\fB\-m45\fR" 4
.IX Item "-m45"
Generate code for a \s-1PDP\-11/45\s0.  This is the default.
.IP "\fB\-m10\fR" 4
.IX Item "-m10"
Generate code for a \s-1PDP\-11/10\s0.
.IP "\fB\-mbcopy\-builtin\fR" 4
.IX Item "-mbcopy-builtin"
Use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory.  This is the
default.
.IP "\fB\-mbcopy\fR" 4
.IX Item "-mbcopy"
Do not use inline \f(CW\*(C`movmemhi\*(C'\fR patterns for copying memory.
.IP "\fB\-mint16\fR" 4
.IX Item "-mint16"
.PD 0
.IP "\fB\-mno\-int32\fR" 4
.IX Item "-mno-int32"
.PD
Use 16\-bit \f(CW\*(C`int\*(C'\fR.  This is the default.
.IP "\fB\-mint32\fR" 4
.IX Item "-mint32"
.PD 0
.IP "\fB\-mno\-int16\fR" 4
.IX Item "-mno-int16"
.PD
Use 32\-bit \f(CW\*(C`int\*(C'\fR.
.IP "\fB\-mfloat64\fR" 4
.IX Item "-mfloat64"
.PD 0
.IP "\fB\-mno\-float32\fR" 4
.IX Item "-mno-float32"
.PD
Use 64\-bit \f(CW\*(C`float\*(C'\fR.  This is the default.
.IP "\fB\-mfloat32\fR" 4
.IX Item "-mfloat32"
.PD 0
.IP "\fB\-mno\-float64\fR" 4
.IX Item "-mno-float64"
.PD
Use 32\-bit \f(CW\*(C`float\*(C'\fR.
.IP "\fB\-mabshi\fR" 4
.IX Item "-mabshi"
Use \f(CW\*(C`abshi2\*(C'\fR pattern.  This is the default.
.IP "\fB\-mno\-abshi\fR" 4
.IX Item "-mno-abshi"
Do not use \f(CW\*(C`abshi2\*(C'\fR pattern.
.IP "\fB\-mbranch\-expensive\fR" 4
.IX Item "-mbranch-expensive"
Pretend that branches are expensive.  This is for experimenting with
code generation only.
.IP "\fB\-mbranch\-cheap\fR" 4
.IX Item "-mbranch-cheap"
Do not pretend that branches are expensive.  This is the default.
.IP "\fB\-msplit\fR" 4
.IX Item "-msplit"
Generate code for a system with split I&D.
.IP "\fB\-mno\-split\fR" 4
.IX Item "-mno-split"
Generate code for a system without split I&D.  This is the default.
.IP "\fB\-munix\-asm\fR" 4
.IX Item "-munix-asm"
Use Unix assembler syntax.  This is the default when configured for
\&\fBpdp11\-*\-bsd\fR.
.IP "\fB\-mdec\-asm\fR" 4
.IX Item "-mdec-asm"
Use \s-1DEC\s0 assembler syntax.  This is the default when configured for any
\&\s-1PDP\-11\s0 target other than \fBpdp11\-*\-bsd\fR.
.PP
\fIPowerPC Options\fR
.IX Subsection "PowerPC Options"
.PP
These are listed under
.PP
\fI\s-1IBM\s0 \s-1RS/6000\s0 and PowerPC Options\fR
.IX Subsection "IBM RS/6000 and PowerPC Options"
.PP
These \fB\-m\fR options are defined for the \s-1IBM\s0 \s-1RS/6000\s0 and PowerPC:
.IP "\fB\-mpower\fR" 4
.IX Item "-mpower"
.PD 0
.IP "\fB\-mno\-j^k^l^m^n^o^p^q^r^s^t^u^v^w^x^y^z^{^|^}^~^^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^�^power\fR" 4
.IX Item "-mno-power"
.IP "\fB\-mpower2\fR" 4
.IX Item "-mpower2"
.IP "\fB\-mno\-power2\fR" 4
.IX Item "-mno-power2"
.IP "\fB\-mpowerpc\fR" 4
.IX Item "-mpowerpc"
.IP "\fB\-mno\-powerpc\fR" 4
.IX Item "-mno-powerpc"
.IP "\fB\-mpowerpc\-gpopt\fR" 4
.IX Item "-mpowerpc-gpopt"
.IP "\fB\-mno\-powerpc\-gpopt\fR" 4
.IX Item "-mno-powerpc-gpopt"
.IP "\fB\-mpowerpc\-gfxopt\fR" 4
.IX Item "-mpowerpc-gfxopt"
.IP "\fB\-mno\-powerpc\-gfxopt\fR" 4
.IX Item "-mno-powerpc-gfxopt"
.IP "\fB\-mpowerpc64\fR" 4
.IX Item "-mpowerpc64"
.IP "\fB\-mno\-powerpc64\fR" 4
.IX Item "-mno-powerpc64"
.IP "\fB\-mmfcrf\fR" 4
.IX Item "-mmfcrf"
.IP "\fB\-mno\-mfcrf\fR" 4
.IX Item "-mno-mfcrf"
.IP "\fB\-mpopcntb\fR" 4
.IX Item "-mpopcntb"
.IP "\fB\-mno\-popcntb\fR" 4
.IX Item "-mno-popcntb"
.IP "\fB\-mfprnd\fR" 4
.IX Item "-mfprnd"
.IP "\fB\-mno\-fprnd\fR" 4
.IX Item "-mno-fprnd"
.IP "\fB\-mcmpb\fR" 4
.IX Item "-mcmpb"
.IP "\fB\-mno\-cmpb\fR" 4
.IX Item "-mno-cmpb"
.IP "\fB\-mmfpgpr\fR" 4
.IX Item "-mmfpgpr"
.IP "\fB\-mno\-mfpgpr\fR" 4
.IX Item "-mno-mfpgpr"
.IP "\fB\-mhard\-dfp\fR" 4
.IX Item "-mhard-dfp"
.IP "\fB\-mno\-hard\-dfp\fR" 4
.IX Item "-mno-hard-dfp"
.PD
\&\s-1GCC\s0 supports two related instruction set architectures for the
\&\s-1RS/6000\s0 and PowerPC.  The \fI\s-1POWER\s0\fR instruction set are those
instructions supported by the \fBrios\fR chip set used in the original
\&\s-1RS/6000\s0 systems and the \fIPowerPC\fR instruction set is the
architecture of the Freescale MPC5xx, MPC6xx, MPC8xx microprocessors, and
the \s-1IBM\s0 4xx, 6xx, and follow-on microprocessors.
.Sp
Neither architecture is a subset of the other.  However there is a
large common subset of instructions supported by both.  An \s-1MQ\s0
register is included in processors supporting the \s-1POWER\s0 architecture.
.Sp
You use these options to specify which instructions are available on the
processor you are using.  The default value of these options is
determined when configuring \s-1GCC\s0.  Specifying the
\&\fB\-mcpu=\fR\fIcpu_type\fR overrides the specification of these
options.  We recommend you use the \fB\-mcpu=\fR\fIcpu_type\fR option
rather than the options listed above.
.Sp
The \fB\-mpower\fR option allows \s-1GCC\s0 to generate instructions that
are found only in the \s-1POWER\s0 architecture and to use the \s-1MQ\s0 register.
Specifying \fB\-mpower2\fR implies \fB\-power\fR and also allows \s-1GCC\s0
to generate instructions that are present in the \s-1POWER2\s0 architecture but
not the original \s-1POWER\s0 architecture.
.Sp
The \fB\-mpowerpc\fR option allows \s-1GCC\s0 to generate instructions that
are found only in the 32\-bit subset of the PowerPC architecture.
Specifying \fB\-mpowerpc\-gpopt\fR implies \fB\-mpowerpc\fR and also allows
\&\s-1GCC\s0 to use the optional PowerPC architecture instructions in the
General Purpose group, including floating-point square root.  Specifying
\&\fB\-mpowerpc\-gfxopt\fR implies \fB\-mpowerpc\fR and also allows \s-1GCC\s0 to
use the optional PowerPC architecture instructions in the Graphics
group, including floating-point select.
.Sp
The \fB\-mmfcrf\fR option allows \s-1GCC\s0 to generate the move from
condition register field instruction implemented on the \s-1POWER4\s0
processor and other processors that support the PowerPC V2.01
architecture.
The \fB\-mpopcntb\fR option allows \s-1GCC\s0 to generate the popcount and
double precision \s-1FP\s0 reciprocal estimate instruction implemented on the
\&\s-1POWER5\s0 processor and other processors that support the PowerPC V2.02
architecture.
The \fB\-mfprnd\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 round to
integer instructions implemented on the \s-1POWER5+\s0 processor and other
processors that support the PowerPC V2.03 architecture.
The \fB\-mcmpb\fR option allows \s-1GCC\s0 to generate the compare bytes
instruction implemented on the \s-1POWER6\s0 processor and other processors
that support the PowerPC V2.05 architecture.
The \fB\-mmfpgpr\fR option allows \s-1GCC\s0 to generate the \s-1FP\s0 move to/from
general purpose register instructions implemented on the \s-1POWER6X\s0
processor and other processors that support the extended PowerPC V2.05
architecture.
The \fB\-mhard\-dfp\fR option allows \s-1GCC\s0 to generate the decimal floating
point instructions implemented on some \s-1POWER\s0 processors.
.Sp
The \fB\-mpowerpc64\fR option allows \s-1GCC\s0 to generate the additional
64\-bit instructions that are found in the full PowerPC64 architecture
and to treat GPRs as 64\-bit, doubleword quantities.  \s-1GCC\s0 defaults to
\&\fB\-mno\-powerpc64\fR.
.Sp
If you specify both \fB\-mno\-power\fR and \fB\-mno\-powerpc\fR, \s-1GCC\s0
will use only the instructions in the common subset of both
architectures plus some special \s-1AIX\s0 common-mode calls, and will not use
the \s-1MQ\s0 register.  Specifying both \fB\-mpower\fR and \fB\-mpowerpc\fR
permits \s-1GCC\s0 to use any instruction from either architecture and to
allow use of the \s-1MQ\s0 register; specify this for the Motorola \s-1MPC601\s0.
.IP "\fB\-mnew\-mnemonics\fR" 4
.IX Item "-mnew-mnemonics"
.PD 0
.IP "\fB\-mold\-mnemonics\fR" 4
.IX Item "-mold-mnemonics"
.PD
Select which mnemonics to use in the generated assembler code.  With
\&\fB\-mnew\-mnemonics\fR, \s-1GCC\s0 uses the assembler mnemonics defined for
the PowerPC architecture.  With \fB\-mold\-mnemonics\fR it uses the
assembler mnemonics defined for the \s-1POWER\s0 architecture.  Instructions
defined in only one architecture have only one mnemonic; \s-1GCC\s0 uses that
mnemonic irrespective of which of these options is specified.
.Sp
\&\s-1GCC\s0 defaults to the mnemonics appropriate for the architecture in
use.  Specifying \fB\-mcpu=\fR\fIcpu_type\fR sometimes overrides the
value of these option.  Unless you are building a cross-compiler, you
should normally not specify either \fB\-mnew\-mnemonics\fR or
\&\fB\-mold\-mnemonics\fR, but should instead accept the default.
.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set architecture type, register usage, choice of mnemonics, and
instruction scheduling parameters for machine type \fIcpu_type\fR.
Supported values for \fIcpu_type\fR are \fB401\fR, \fB403\fR,
\&\fB405\fR, \fB405fp\fR, \fB440\fR, \fB440fp\fR, \fB505\fR,
\&\fB601\fR, \fB602\fR, \fB603\fR, \fB603e\fR, \fB604\fR,
\&\fB604e\fR, \fB620\fR, \fB630\fR, \fB740\fR, \fB7400\fR,
\&\fB7450\fR, \fB750\fR, \fB801\fR, \fB821\fR, \fB823\fR,
\&\fB860\fR, \fB970\fR, \fB8540\fR, \fBec603e\fR, \fBG3\fR,
\&\fBG4\fR, \fBG5\fR, \fBpower\fR, \fBpower2\fR, \fBpower3\fR,
\&\fBpower4\fR, \fBpower5\fR, \fBpower5+\fR, \fBpower6\fR,
\&\fBpower6x\fR, \fBcommon\fR, \fBpowerpc\fR, \fBpowerpc64\fR,
\&\fBrios\fR, \fBrios1\fR, \fBrios2\fR, \fBrsc\fR, and \fBrs64\fR.
.Sp
\&\fB\-mcpu=common\fR selects a completely generic processor.  Code
generated under this option will run on any \s-1POWER\s0 or PowerPC processor.
\&\s-1GCC\s0 will use only the instructions in the common subset of both
architectures, and will not use the \s-1MQ\s0 register.  \s-1GCC\s0 assumes a generic
processor model for scheduling purposes.
.Sp
\&\fB\-mcpu=power\fR, \fB\-mcpu=power2\fR, \fB\-mcpu=powerpc\fR, and
\&\fB\-mcpu=powerpc64\fR specify generic \s-1POWER\s0, \s-1POWER2\s0, pure 32\-bit
PowerPC (i.e., not \s-1MPC601\s0), and 64\-bit PowerPC architecture machine
types, with an appropriate, generic processor model assumed for
scheduling purposes.
.Sp
The other options specify a specific processor.  Code generated under
those options will run best on that processor, and may not run at all on
others.
.Sp
The \fB\-mcpu\fR options automatically enable or disable the
following options:
.Sp
\&\fB\-maltivec  \-mfprnd  \-mhard\-float  \-mmfcrf  \-mmultiple 
\&\-mnew\-mnemonics  \-mpopcntb  \-mpower  \-mpower2  \-mpowerpc64 
\&\-mpowerpc\-gpopt  \-mpowerpc\-gfxopt  \-mstring  \-mmulhw  \-mdlmzb  \-mmfpgpr\fR
.Sp
The particular options set for any particular \s-1CPU\s0 will vary between
compiler versions, depending on what setting seems to produce optimal
code for that \s-1CPU\s0; it doesn't necessarily reflect the actual hardware's
capabilities.  If you wish to set an individual option to a particular
value, you may specify it after the \fB\-mcpu\fR option, like
\&\fB\-mcpu=970 \-mno\-altivec\fR.
.Sp
On \s-1AIX\s0, the \fB\-maltivec\fR and \fB\-mpowerpc64\fR options are
not enabled or disabled by the \fB\-mcpu\fR option at present because
\&\s-1AIX\s0 does not have full support for these options.  You may still
enable or disable them individually if you're sure it'll work in your
environment.
.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set the instruction scheduling parameters for machine type
\&\fIcpu_type\fR, but do not set the architecture type, register usage, or
choice of mnemonics, as \fB\-mcpu=\fR\fIcpu_type\fR would.  The same
values for \fIcpu_type\fR are used for \fB\-mtune\fR as for
\&\fB\-mcpu\fR.  If both are specified, the code generated will use the
architecture, registers, and mnemonics set by \fB\-mcpu\fR, but the
scheduling parameters set by \fB\-mtune\fR.
.IP "\fB\-mswdiv\fR" 4
.IX Item "-mswdiv"
.PD 0
.IP "\fB\-mno\-swdiv\fR" 4
.IX Item "-mno-swdiv"
.PD
Generate code to compute division as reciprocal estimate and iterative
refinement, creating opportunities for increased throughput.  This
feature requires: optional PowerPC Graphics instruction set for single
precision and \s-1FRE\s0 instruction for double precision, assuming divides
cannot generate user-visible traps, and the domain values not include
Infinities, denormals or zero denominator.
.IP "\fB\-maltivec\fR" 4
.IX Item "-maltivec"
.PD 0
.IP "\fB\-mno\-altivec\fR" 4
.IX Item "-mno-altivec"
.PD
Generate code that uses (does not use) AltiVec instructions, and also
enable the use of built-in functions that allow more direct access to
the AltiVec instruction set.  You may also need to set
\&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0
enhancements.
.IP "\fB\-mvrsave\fR" 4
.IX Item "-mvrsave"
.PD 0
.IP "\fB\-mno\-vrsave\fR" 4
.IX Item "-mno-vrsave"
.PD
Generate \s-1VRSAVE\s0 instructions when generating AltiVec code.
.IP "\fB\-msecure\-plt\fR" 4
.IX Item "-msecure-plt"
Generate code that allows ld and ld.so to build executables and shared
libraries with non-exec .plt and .got sections.  This is a PowerPC
32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-mbss\-plt\fR" 4
.IX Item "-mbss-plt"
Generate code that uses a \s-1BSS\s0 .plt section that ld.so fills in, and
requires .plt and .got sections that are both writable and executable.
This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option.
.IP "\fB\-misel\fR" 4
.IX Item "-misel"
.PD 0
.IP "\fB\-mno\-isel\fR" 4
.IX Item "-mno-isel"
.PD
This switch enables or disables the generation of \s-1ISEL\s0 instructions.
.IP "\fB\-misel=\fR\fIyes/no\fR" 4
.IX Item "-misel=yes/no"
This switch has been deprecated.  Use \fB\-misel\fR and
\&\fB\-mno\-isel\fR instead.
.IP "\fB\-mspe\fR" 4
.IX Item "-mspe"
.PD 0
.IP "\fB\-mno\-spe\fR" 4
.IX Item "-mno-spe"
.PD
This switch enables or disables the generation of \s-1SPE\s0 simd
instructions.
.IP "\fB\-mpaired\fR" 4
.IX Item "-mpaired"
.PD 0
.IP "\fB\-mno\-paired\fR" 4
.IX Item "-mno-paired"
.PD
This switch enables or disables the generation of \s-1PAIRED\s0 simd
instructions.
.IP "\fB\-mspe=\fR\fIyes/no\fR" 4
.IX Item "-mspe=yes/no"
This option has been deprecated.  Use \fB\-mspe\fR and
\&\fB\-mno\-spe\fR instead.
.IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4
.IX Item "-mfloat-gprs=yes/single/double/no"
.PD 0
.IP "\fB\-mfloat\-gprs\fR" 4
.IX Item "-mfloat-gprs"
.PD
This switch enables or disables the generation of floating point
operations on the general purpose registers for architectures that
support it.
.Sp
The argument \fIyes\fR or \fIsingle\fR enables the use of
single-precision floating point operations.
.Sp
The argument \fIdouble\fR enables the use of single and
double-precision floating point operations.
.Sp
The argument \fIno\fR disables floating point operations on the
general purpose registers.
.Sp
This option is currently only available on the MPC854x.
.IP "\fB\-m32\fR" 4
.IX Item "-m32"
.PD 0
.IP "\fB\-m64\fR" 4
.IX Item "-m64"
.PD
Generate code for 32\-bit or 64\-bit environments of Darwin and \s-1SVR4\s0
targets (including GNU/Linux).  The 32\-bit environment sets int, long
and pointer to 32 bits and generates code that runs on any PowerPC
variant.  The 64\-bit environment sets int to 32 bits and long and
pointer to 64 bits, and generates code for PowerPC64, as for
\&\fB\-mpowerpc64\fR.
.IP "\fB\-mfull\-toc\fR" 4
.IX Item "-mfull-toc"
.PD 0
.IP "\fB\-mno\-fp\-in\-toc\fR" 4
.IX Item "-mno-fp-in-toc"
.IP "\fB\-mno\-sum\-in\-toc\fR" 4
.IX Item "-mno-sum-in-toc"
.IP "\fB\-mminimal\-toc\fR" 4
.IX Item "-mminimal-toc"
.PD
Modify generation of the \s-1TOC\s0 (Table Of Contents), which is created for
every executable file.  The \fB\-mfull\-toc\fR option is selected by
default.  In that case, \s-1GCC\s0 will allocate at least one \s-1TOC\s0 entry for
each unique non-automatic variable reference in your program.  \s-1GCC\s0
will also place floating-point constants in the \s-1TOC\s0.  However, only
16,384 entries are available in the \s-1TOC\s0.
.Sp
If you receive a linker error message that saying you have overflowed
the available \s-1TOC\s0 space, you can reduce the amount of \s-1TOC\s0 space used
with the \fB\-mno\-fp\-in\-toc\fR and \fB\-mno\-sum\-in\-toc\fR options.
\&\fB\-mno\-fp\-in\-toc\fR prevents \s-1GCC\s0 from putting floating-point
constants in the \s-1TOC\s0 and \fB\-mno\-sum\-in\-toc\fR forces \s-1GCC\s0 to
generate code to calculate the sum of an address and a constant at
run-time instead of putting that sum into the \s-1TOC\s0.  You may specify one
or both of these options.  Each causes \s-1GCC\s0 to produce very slightly
slower and larger code at the expense of conserving \s-1TOC\s0 space.
.Sp
If you still run out of space in the \s-1TOC\s0 even when you specify both of
these options, specify \fB\-mminimal\-toc\fR instead.  This option causes
\&\s-1GCC\s0 to make only one \s-1TOC\s0 entry for every file.  When you specify this
option, \s-1GCC\s0 will produce code that is slower and larger but which
uses extremely little \s-1TOC\s0 space.  You may wish to use this option
only on files that contain less frequently executed code.
.IP "\fB\-maix64\fR" 4
.IX Item "-maix64"
.PD 0
.IP "\fB\-maix32\fR" 4
.IX Item "-maix32"
.PD
Enable 64\-bit \s-1AIX\s0 \s-1ABI\s0 and calling convention: 64\-bit pointers, 64\-bit
\&\f(CW\*(C`long\*(C'\fR type, and the infrastructure needed to support them.
Specifying \fB\-maix64\fR implies \fB\-mpowerpc64\fR and
\&\fB\-mpowerpc\fR, while \fB\-maix32\fR disables the 64\-bit \s-1ABI\s0 and
implies \fB\-mno\-powerpc64\fR.  \s-1GCC\s0 defaults to \fB\-maix32\fR.
.IP "\fB\-mxl\-compat\fR" 4
.IX Item "-mxl-compat"
.PD 0
.IP "\fB\-mno\-xl\-compat\fR" 4
.IX Item "-mno-xl-compat"
.PD
Produce code that conforms more closely to \s-1IBM\s0 \s-1XL\s0 compiler semantics
when using AIX-compatible \s-1ABI\s0.  Pass floating-point arguments to
prototyped functions beyond the register save area (\s-1RSA\s0) on the stack
in addition to argument FPRs.  Do not assume that most significant
double in 128\-bit long double value is properly rounded when comparing
values and converting to double.  Use \s-1XL\s0 symbol names for long double
support routines.
.Sp
The \s-1AIX\s0 calling convention was extended but not initially documented to
handle an obscure K&R C case of calling a function that takes the
address of its arguments with fewer arguments than declared.  \s-1IBM\s0 \s-1XL\s0
compilers access floating point arguments which do not fit in the
\&\s-1RSA\s0 from the stack when a subroutine is compiled without
optimization.  Because always storing floating-point arguments on the
stack is inefficient and rarely needed, this option is not enabled by
default and only is necessary when calling subroutines compiled by \s-1IBM\s0
\&\s-1XL\s0 compilers without optimization.
.IP "\fB\-mpe\fR" 4
.IX Item "-mpe"
Support \fI\s-1IBM\s0 \s-1RS/6000\s0 \s-1SP\s0\fR \fIParallel Environment\fR (\s-1PE\s0).  Link an
application written to use message passing with special startup code to
enable the application to run.  The system must have \s-1PE\s0 installed in the
standard location (\fI/usr/lpp/ppe.poe/\fR), or the \fIspecs\fR file
must be overridden with the \fB\-specs=\fR option to specify the
appropriate directory location.  The Parallel Environment does not
support threads, so the \fB\-mpe\fR option and the \fB\-pthread\fR
option are incompatible.
.IP "\fB\-malign\-natural\fR" 4
.IX Item "-malign-natural"
.PD 0
.IP "\fB\-malign\-power\fR" 4
.IX Item "-malign-power"
.PD
On \s-1AIX\s0, 32\-bit Darwin, and 64\-bit PowerPC GNU/Linux, the option
\&\fB\-malign\-natural\fR overrides the ABI-defined alignment of larger
types, such as floating-point doubles, on their natural size-based boundary.
The option \fB\-malign\-power\fR instructs \s-1GCC\s0 to follow the ABI-specified
alignment rules.  \s-1GCC\s0 defaults to the standard alignment defined in the \s-1ABI\s0.
.Sp
On 64\-bit Darwin, natural alignment is the default, and \fB\-malign\-power\fR
is not supported.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
.PD 0
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
.PD
Generate code that does not use (uses) the floating-point register set.
Software floating point emulation is provided if you use the
\&\fB\-msoft\-float\fR option, and pass the option to \s-1GCC\s0 when linking.
.IP "\fB\-mmultiple\fR" 4
.IX Item "-mmultiple"
.PD 0
.IP "\fB\-mno\-multiple\fR" 4
.IX Item "-mno-multiple"
.PD
Generate code that uses (does not use) the load multiple word
instructions and the store multiple word instructions.  These
instructions are generated by default on \s-1POWER\s0 systems, and not
generated on PowerPC systems.  Do not use \fB\-mmultiple\fR on little
endian PowerPC systems, since those instructions do not work when the
processor is in little endian mode.  The exceptions are \s-1PPC740\s0 and
\&\s-1PPC750\s0 which permit the instructions usage in little endian mode.
.IP "\fB\-mstring\fR" 4
.IX Item "-mstring"
.PD 0
.IP "\fB\-mno\-string\fR" 4
.IX Item "-mno-string"
.PD
Generate code that uses (does not use) the load string instructions
and the store string word instructions to save multiple registers and
do small block moves.  These instructions are generated by default on
\&\s-1POWER\s0 systems, and not generated on PowerPC systems.  Do not use
\&\fB\-mstring\fR on little endian PowerPC systems, since those
instructions do not work when the processor is in little endian mode.
The exceptions are \s-1PPC740\s0 and \s-1PPC750\s0 which permit the instructions
usage in little endian mode.
.IP "\fB\-mupdate\fR" 4
.IX Item "-mupdate"
.PD 0
.IP "\fB\-mno\-update\fR" 4
.IX Item "-mno-update"
.PD
Generate code that uses (does not use) the load or store instructions
that update the base register to the address of the calculated memory
location.  These instructions are generated by default.  If you use
\&\fB\-mno\-update\fR, there is a small window between the time that the
stack pointer is updated and the address of the previous frame is
stored, which means code that walks the stack frame across interrupts or
signals may get corrupted data.
.IP "\fB\-mfused\-madd\fR" 4
.IX Item "-mfused-madd"
.PD 0
.IP "\fB\-mno\-fused\-madd\fR" 4
.IX Item "-mno-fused-madd"
.PD
Generate code that uses (does not use) the floating point multiply and
accumulate instructions.  These instructions are generated by default if
hardware floating is used.
.IP "\fB\-mmulhw\fR" 4
.IX Item "-mmulhw"
.PD 0
.IP "\fB\-mno\-mulhw\fR" 4
.IX Item "-mno-mulhw"
.PD
Generate code that uses (does not use) the half-word multiply and
multiply-accumulate instructions on the \s-1IBM\s0 405 and 440 processors.
These instructions are generated by default when targetting those
processors.
.IP "\fB\-mdlmzb\fR" 4
.IX Item "-mdlmzb"
.PD 0
.IP "\fB\-mno\-dlmzb\fR" 4
.IX Item "-mno-dlmzb"
.PD
Generate code that uses (does not use) the string-search \fBdlmzb\fR
instruction on the \s-1IBM\s0 405 and 440 processors.  This instruction is
generated by default when targetting those processors.
.IP "\fB\-mno\-bit\-align\fR" 4
.IX Item "-mno-bit-align"
.PD 0
.IP "\fB\-mbit\-align\fR" 4
.IX Item "-mbit-align"
.PD
On System V.4 and embedded PowerPC systems do not (do) force structures
and unions that contain bit-fields to be aligned to the base type of the
bit-field.
.Sp
For example, by default a structure containing nothing but 8
\&\f(CW\*(C`unsigned\*(C'\fR bit-fields of length 1 would be aligned to a 4 byte
boundary and have a size of 4 bytes.  By using \fB\-mno\-bit\-align\fR,
the structure would be aligned to a 1 byte boundary and be one byte in
size.
.IP "\fB\-mno\-strict\-align\fR" 4
.IX Item "-mno-strict-align"
.PD 0
.IP "\fB\-mstrict\-align\fR" 4
.IX Item "-mstrict-align"
.PD
On System V.4 and embedded PowerPC systems do not (do) assume that
unaligned memory references will be handled by the system.
.IP "\fB\-mrelocatable\fR" 4
.IX Item "-mrelocatable"
.PD 0
.IP "\fB\-mno\-relocatable\fR" 4
.IX Item "-mno-relocatable"
.PD
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime.  If you
use \fB\-mrelocatable\fR on any module, all objects linked together must
be compiled with \fB\-mrelocatable\fR or \fB\-mrelocatable\-lib\fR.
.IP "\fB\-mrelocatable\-lib\fR" 4
.IX Item "-mrelocatable-lib"
.PD 0
.IP "\fB\-mno\-relocatable\-lib\fR" 4
.IX Item "-mno-relocatable-lib"
.PD
On embedded PowerPC systems generate code that allows (does not allow)
the program to be relocated to a different address at runtime.  Modules
compiled with \fB\-mrelocatable\-lib\fR can be linked with either modules
compiled without \fB\-mrelocatable\fR and \fB\-mrelocatable\-lib\fR or
with modules compiled with the \fB\-mrelocatable\fR options.
.IP "\fB\-mno\-toc\fR" 4
.IX Item "-mno-toc"
.PD 0
.IP "\fB\-mtoc\fR" 4
.IX Item "-mtoc"
.PD
On System V.4 and embedded PowerPC systems do not (do) assume that
register 2 contains a pointer to a global area pointing to the addresses
used in the program.
.IP "\fB\-mlittle\fR" 4
.IX Item "-mlittle"
.PD 0
.IP "\fB\-mlittle\-endian\fR" 4
.IX Item "-mlittle-endian"
.PD
On System V.4 and embedded PowerPC systems compile code for the
processor in little endian mode.  The \fB\-mlittle\-endian\fR option is
the same as \fB\-mlittle\