nnot
be reliably used inside one program.  The default is
\&\fB\-mno\-thumb\-interwork\fR, since slightly larger code is generated
when \fB\-mthumb\-interwork\fR is specified.
.IP "\fB\-mno\-sched\-prolog\fR" 4
.IX Item "-mno-sched-prolog"
Prevent the reordering of instructions in the function prolog, or the
merging of those instruction with the instructions in the function's
body.  This means that all functions will start with a recognizable set
of instructions (or in fact one of a choice from a small set of
different function prologues), and this information can be used to
locate the start if functions inside an executable piece of code.  The
default is \fB\-msched\-prolog\fR.
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
Generate output containing floating point instructions.  This is the
default.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Generate output containing library calls for floating point.
\&\fBWarning:\fR the requisite libraries are not available for all \s-1ARM\s0
targets.  Normally the facilities of the machine's usual C compiler are
used, but this cannot be done directly in cross-compilation.  You must make
your own arrangements to provide suitable library functions for
cross-compilation.
.Sp
\&\fB\-msoft\-float\fR changes the calling convention in the output file;
therefore, it is only useful if you compile \fIall\fR of a program with
this option.  In particular, you need to compile \fIlibgcc.a\fR, the
library that comes with \s-1GCC\s0, with \fB\-msoft\-float\fR in order for
this to work.
.IP "\fB\-mfloat\-abi=\fR\fIname\fR" 4
.IX Item "-mfloat-abi=name"
Specifies which \s-1ABI\s0 to use for floating point values.  Permissible values
are: \fBsoft\fR, \fBsoftfp\fR and \fBhard\fR.
.Sp
\&\fBsoft\fR and \fBhard\fR are equivalent to \fB\-msoft\-float\fR
and \fB\-mhard\-float\fR respectively.  \fBsoftfp\fR allows the generation
of floating point instructions, but still uses the soft-float calling
conventions.
.IP "\fB\-mlittle\-endian\fR" 4
.IX Item "-mlittle-endian"
Generate code for a processor running in little-endian mode.  This is
the default for all standard configurations.
.IP "\fB\-mbig\-endian\fR" 4
.IX Item "-mbig-endian"
Generate code for a processor running in big-endian mode; the default is
to compile code for a little-endian processor.
.IP "\fB\-mwords\-little\-endian\fR" 4
.IX Item "-mwords-little-endian"
This option only applies when generating code for big-endian processors.
Generate code for a little-endian word order but a big-endian byte
order.  That is, a byte order of the form \fB32107654\fR.  Note: this
option should only be used if you require compatibility with code for
big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to
2.8.
.IP "\fB\-mcpu=\fR\fIname\fR" 4
.IX Item "-mcpu=name"
This specifies the name of the target \s-1ARM\s0 processor.  \s-1GCC\s0 uses this name
to determine what kind of instructions it can emit when generating
assembly code.  Permissible names are: \fBarm2\fR, \fBarm250\fR,
\&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR,
\&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR,
\&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR,
\&\fBarm700i\fR, \fBarm710\fR, \fBarm710c\fR, \fBarm7100\fR,
\&\fBarm7500\fR, \fBarm7500fe\fR, \fBarm7tdmi\fR, \fBarm7tdmi\-s\fR,
\&\fBarm8\fR, \fBstrongarm\fR, \fBstrongarm110\fR, \fBstrongarm1100\fR,
\&\fBarm8\fR, \fBarm810\fR, \fBarm9\fR, \fBarm9e\fR, \fBarm920\fR,
\&\fBarm920t\fR, \fBarm922t\fR, \fBarm946e\-s\fR, \fBarm966e\-s\fR,
\&\fBarm968e\-s\fR, \fBarm926ej\-s\fR, \fBarm940t\fR, \fBarm9tdmi\fR,
\&\fBarm10tdmi\fR, \fBarm1020t\fR, \fBarm1026ej\-s\fR,
\&\fBarm10e\fR, \fBarm1020e\fR, \fBarm1022e\fR,
\&\fBarm1136j\-s\fR, \fBarm1136jf\-s\fR, \fBmpcore\fR, \fBmpcorenovfp\fR,
\&\fBarm1156t2\-s\fR, \fBarm1176jz\-s\fR, \fBarm1176jzf\-s\fR,
\&\fBcortex\-a8\fR, \fBcortex\-r4\fR, \fBcortex\-m3\fR,
\&\fBxscale\fR, \fBiwmmxt\fR, \fBep9312\fR.
.IP "\fB\-mtune=\fR\fIname\fR" 4
.IX Item "-mtune=name"
This option is very similar to the \fB\-mcpu=\fR option, except that
instead of specifying the actual target processor type, and hence
restricting which instructions can be used, it specifies that \s-1GCC\s0 should
tune the performance of the code as if the target were of the type
specified in this option, but still choosing the instructions that it
will generate based on the cpu specified by a \fB\-mcpu=\fR option.
For some \s-1ARM\s0 implementations better performance can be obtained by using
this option.
.IP "\fB\-march=\fR\fIname\fR" 4
.IX Item "-march=name"
This specifies the name of the target \s-1ARM\s0 architecture.  \s-1GCC\s0 uses this
name to determine what kind of instructions it can emit when generating
assembly code.  This option can be used in conjunction with or instead
of the \fB\-mcpu=\fR option.  Permissible names are: \fBarmv2\fR,
\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR,
\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5te\fR, \fBarmv6\fR, \fBarmv6j\fR,
\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv7\fR, \fBarmv7\-a\fR,
\&\fBarmv7\-r\fR, \fBarmv7\-m\fR, \fBiwmmxt\fR, \fBep9312\fR.
.IP "\fB\-mfpu=\fR\fIname\fR" 4
.IX Item "-mfpu=name"
.PD 0
.IP "\fB\-mfpe=\fR\fInumber\fR" 4
.IX Item "-mfpe=number"
.IP "\fB\-mfp=\fR\fInumber\fR" 4
.IX Item "-mfp=number"
.PD
This specifies what floating point hardware (or hardware emulation) is
available on the target.  Permissible names are: \fBfpa\fR, \fBfpe2\fR,
\&\fBfpe3\fR, \fBmaverick\fR, \fBvfp\fR.  \fB\-mfp\fR and \fB\-mfpe\fR
are synonyms for \fB\-mfpu\fR=\fBfpe\fR\fInumber\fR, for compatibility
with older versions of \s-1GCC\s0.
.Sp
If \fB\-msoft\-float\fR is specified this specifies the format of
floating point values.
.IP "\fB\-mstructure\-size\-boundary=\fR\fIn\fR" 4
.IX Item "-mstructure-size-boundary=n"
The size of all structures and unions will be rounded up to a multiple
of the number of bits set by this option.  Permissible values are 8, 32
and 64.  The default value varies for different toolchains.  For the \s-1COFF\s0
targeted toolchain the default value is 8.  A value of 64 is only allowed
if the underlying \s-1ABI\s0 supports it.
.Sp
Specifying the larger number can produce faster, more efficient code, but
can also increase the size of the program.  Different values are potentially
incompatible.  Code compiled with one value cannot necessarily expect to
work with code or libraries compiled with another value, if they exchange
information using structures or unions.
.IP "\fB\-mabort\-on\-noreturn\fR" 4
.IX Item "-mabort-on-noreturn"
Generate a call to the function \f(CW\*(C`abort\*(C'\fR at the end of a
\&\f(CW\*(C`noreturn\*(C'\fR function.  It will be executed if the function tries to
return.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.IP "\fB\-mno\-long\-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Tells the compiler to perform function calls by first loading the
address of the function into a register and then performing a subroutine
call on this register.  This switch is needed if the target function
will lie outside of the 64 megabyte addressing range of the offset based
version of subroutine call instruction.
.Sp
Even if this switch is enabled, not all function calls will be turned
into long calls.  The heuristic is that static functions, functions
which have the \fBshort-call\fR attribute, functions that are inside
the scope of a \fB#pragma no_long_calls\fR directive and functions whose
definitions have already been compiled within the current compilation
unit, will not be turned into long calls.  The exception to this rule is
that weak function definitions, functions with the \fBlong-call\fR
attribute or the \fBsection\fR attribute, and functions that are within
the scope of a \fB#pragma long_calls\fR directive, will always be
turned into long calls.
.Sp
This feature is not enabled by default.  Specifying
\&\fB\-mno\-long\-calls\fR will restore the default behavior, as will
placing the function calls within the scope of a \fB#pragma
long_calls_off\fR directive.  Note these switches have no effect on how
the compiler generates code to handle function calls via function
pointers.
.IP "\fB\-mnop\-fun\-dllimport\fR" 4
.IX Item "-mnop-fun-dllimport"
Disable support for the \f(CW\*(C`dllimport\*(C'\fR attribute.
.IP "\fB\-msingle\-pic\-base\fR" 4
.IX Item "-msingle-pic-base"
Treat the register used for \s-1PIC\s0 addressing as read-only, rather than
loading it in the prologue for each function.  The run-time system is
responsible for initializing this register with an appropriate value
before execution begins.
.IP "\fB\-mpic\-register=\fR\fIreg\fR" 4
.IX Item "-mpic-register=reg"
Specify the register to be used for \s-1PIC\s0 addressing.  The default is R10
unless stack-checking is enabled, when R9 is used.
.IP "\fB\-mcirrus\-fix\-invalid\-insns\fR" 4
.IX Item "-mcirrus-fix-invalid-insns"
Insert NOPs into the instruction stream to in order to work around
problems with invalid Maverick instruction combinations.  This option
is only valid if the \fB\-mcpu=ep9312\fR option has been used to
enable generation of instructions for the Cirrus Maverick floating
point co-processor.  This option is not enabled by default, since the
problem is only present in older Maverick implementations.  The default
can be re-enabled by use of the \fB\-mno\-cirrus\-fix\-invalid\-insns\fR
switch.
.IP "\fB\-mpoke\-function\-name\fR" 4
.IX Item "-mpoke-function-name"
Write the name of each function into the text section, directly
preceding the function prologue.  The generated code is similar to this:
.Sp
.Vb 9
\&             t0
\&                 .ascii "arm_poke_function_name", 0
\&                 .align
\&             t1
\&                 .word 0xff000000 + (t1 \- t0)
\&             arm_poke_function_name
\&                 mov     ip, sp
\&                 stmfd   sp!, {fp, ip, lr, pc}
\&                 sub     fp, ip, #4
.Ve
.Sp
When performing a stack backtrace, code can inspect the value of
\&\f(CW\*(C`pc\*(C'\fR stored at \f(CW\*(C`fp + 0\*(C'\fR.  If the trace function then looks at
location \f(CW\*(C`pc \- 12\*(C'\fR and the top 8 bits are set, then we know that
there is a function name embedded immediately preceding this location
and has length \f(CW\*(C`((pc[\-3]) & 0xff000000)\*(C'\fR.
.IP "\fB\-mthumb\fR" 4
.IX Item "-mthumb"
Generate code for the Thumb instruction set.  The default is to
use the 32\-bit \s-1ARM\s0 instruction set.
This option automatically enables either 16\-bit Thumb\-1 or
mixed 16/32\-bit Thumb\-2 instructions based on the \fB\-mcpu=\fR\fIname\fR
and \fB\-march=\fR\fIname\fR options.
.IP "\fB\-mtpcs\-frame\fR" 4
.IX Item "-mtpcs-frame"
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all non-leaf functions.  (A leaf function is one that does
not call any other functions.)  The default is \fB\-mno\-tpcs\-frame\fR.
.IP "\fB\-mtpcs\-leaf\-frame\fR" 4
.IX Item "-mtpcs-leaf-frame"
Generate a stack frame that is compliant with the Thumb Procedure Call
Standard for all leaf functions.  (A leaf function is one that does
not call any other functions.)  The default is \fB\-mno\-apcs\-leaf\-frame\fR.
.IP "\fB\-mcallee\-super\-interworking\fR" 4
.IX Item "-mcallee-super-interworking"
Gives all externally visible functions in the file being compiled an \s-1ARM\s0
instruction set header which switches to Thumb mode before executing the
rest of the function.  This allows these functions to be called from
non-interworking code.
.IP "\fB\-mcaller\-super\-interworking\fR" 4
.IX Item "-mcaller-super-interworking"
Allows calls via function pointers (including virtual functions) to
execute correctly regardless of whether the target code has been
compiled for interworking or not.  There is a small overhead in the cost
of executing a function pointer if this option is enabled.
.IP "\fB\-mtp=\fR\fIname\fR" 4
.IX Item "-mtp=name"
Specify the access model for the thread local storage pointer.  The valid
models are \fBsoft\fR, which generates calls to \f(CW\*(C`_\|_aeabi_read_tp\*(C'\fR,
\&\fBcp15\fR, which fetches the thread pointer from \f(CW\*(C`cp15\*(C'\fR directly
(supported in the arm6k architecture), and \fBauto\fR, which uses the
best available method for the selected processor.  The default setting is
\&\fBauto\fR.
.PP
\fI\s-1AVR\s0 Options\fR
.IX Subsection "AVR Options"
.PP
These options are defined for \s-1AVR\s0 implementations:
.IP "\fB\-mmcu=\fR\fImcu\fR" 4
.IX Item "-mmcu=mcu"
Specify \s-1ATMEL\s0 \s-1AVR\s0 instruction set or \s-1MCU\s0 type.
.Sp
Instruction set avr1 is for the minimal \s-1AVR\s0 core, not supported by the C
compiler, only for assembler programs (\s-1MCU\s0 types: at90s1200, attiny10,
attiny11, attiny12, attiny15, attiny28).
.Sp
Instruction set avr2 (default) is for the classic \s-1AVR\s0 core with up to
8K program memory space (\s-1MCU\s0 types: at90s2313, at90s2323, attiny22,
at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
at90c8534, at90s8535).
.Sp
Instruction set avr3 is for the classic \s-1AVR\s0 core with up to 128K program
memory space (\s-1MCU\s0 types: atmega103, atmega603, at43usb320, at76c711).
.Sp
Instruction set avr4 is for the enhanced \s-1AVR\s0 core with up to 8K program
memory space (\s-1MCU\s0 types: atmega8, atmega83, atmega85).
.Sp
Instruction set avr5 is for the enhanced \s-1AVR\s0 core with up to 128K program
memory space (\s-1MCU\s0 types: atmega16, atmega161, atmega163, atmega32, atmega323,
atmega64, atmega128, at43usb355, at94k).
.IP "\fB\-msize\fR" 4
.IX Item "-msize"
Output instruction sizes to the asm file.
.IP "\fB\-minit\-stack=\fR\fIN\fR" 4
.IX Item "-minit-stack=N"
Specify the initial stack address, which may be a symbol or numeric value,
\&\fB_\|_stack\fR is the default.
.IP "\fB\-mno\-interrupts\fR" 4
.IX Item "-mno-interrupts"
Generated code is not compatible with hardware interrupts.
Code size will be smaller.
.IP "\fB\-mcall\-prologues\fR" 4
.IX Item "-mcall-prologues"
Functions prologues/epilogues expanded as call to appropriate
subroutines.  Code size will be smaller.
.IP "\fB\-mno\-tablejump\fR" 4
.IX Item "-mno-tablejump"
Do not generate tablejump insns which sometimes increase code size.
.IP "\fB\-mtiny\-stack\fR" 4
.IX Item "-mtiny-stack"
Change only the low 8 bits of the stack pointer.
.IP "\fB\-mint8\fR" 4
.IX Item "-mint8"
Assume int to be 8 bit integer.  This affects the sizes of all types: A
char will be 1 byte, an int will be 1 byte, an long will be 2 bytes
and long long will be 4 bytes.  Please note that this option does not
comply to the C standards, but it will provide you with smaller code
size.
.PP
\fIBlackfin Options\fR
.IX Subsection "Blackfin Options"
.IP "\fB\-mcpu=\fR\fIcpu\fR[\fB\-\fR\fIsirevision\fR]" 4
.IX Item "-mcpu=cpu[-sirevision]"
Specifies the name of the target Blackfin processor.  Currently, \fIcpu\fR
can be one of \fBbf522\fR, \fBbf523\fR, \fBbf524\fR,
\&\fBbf525\fR, \fBbf526\fR, \fBbf527\fR,
\&\fBbf531\fR, \fBbf532\fR, \fBbf533\fR, \fBbf534\fR,
\&\fBbf536\fR, \fBbf537\fR, \fBbf538\fR, \fBbf539\fR,
\&\fBbf542\fR, \fBbf544\fR, \fBbf547\fR, \fBbf548\fR, \fBbf549\fR,
\&\fBbf561\fR.
The optional \fIsirevision\fR specifies the silicon revision of the target
Blackfin processor.  Any workarounds available for the targeted silicon revision
will be enabled.  If \fIsirevision\fR is \fBnone\fR, no workarounds are enabled.
If \fIsirevision\fR is \fBany\fR, all workarounds for the targeted processor
will be enabled.  The \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR macro is defined to two
hexadecimal digits representing the major and minor numbers in the silicon
revision.  If \fIsirevision\fR is \fBnone\fR, the \f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR
is not defined.  If \fIsirevision\fR is \fBany\fR, the
\&\f(CW\*(C`_\|_SILICON_REVISION_\|_\*(C'\fR is defined to be \f(CW0xffff\fR.
If this optional \fIsirevision\fR is not used, \s-1GCC\s0 assumes the latest known
silicon revision of the targeted Blackfin processor.
.Sp
Support for \fBbf561\fR is incomplete.  For \fBbf561\fR,
Only the processor macro is defined.
Without this option, \fBbf532\fR is used as the processor by default.
The corresponding predefined processor macros for \fIcpu\fR is to
be defined.  And for \fBbfin-elf\fR toolchain, this causes the hardware \s-1BSP\s0
provided by libgloss to be linked in if \fB\-msim\fR is not given.
.IP "\fB\-msim\fR" 4
.IX Item "-msim"
Specifies that the program will be run on the simulator.  This causes
the simulator \s-1BSP\s0 provided by libgloss to be linked in.  This option
has effect only for \fBbfin-elf\fR toolchain.
Certain other options, such as \fB\-mid\-shared\-library\fR and
\&\fB\-mfdpic\fR, imply \fB\-msim\fR.
.IP "\fB\-momit\-leaf\-frame\-pointer\fR" 4
.IX Item "-momit-leaf-frame-pointer"
Don't keep the frame pointer in a register for leaf functions.  This
avoids the instructions to save, set up and restore frame pointers and
makes an extra register available in leaf functions.  The option
\&\fB\-fomit\-frame\-pointer\fR removes the frame pointer for all functions
which might make debugging harder.
.IP "\fB\-mspecld\-anomaly\fR" 4
.IX Item "-mspecld-anomaly"
When enabled, the compiler will ensure that the generated code does not
contain speculative loads after jump instructions. If this option is used,
\&\f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_LOADS\*(C'\fR is defined.
.IP "\fB\-mno\-specld\-anomaly\fR" 4
.IX Item "-mno-specld-anomaly"
Don't generate extra code to prevent speculative loads from occurring.
.IP "\fB\-mcsync\-anomaly\fR" 4
.IX Item "-mcsync-anomaly"
When enabled, the compiler will ensure that the generated code does not
contain \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions too soon after conditional branches.
If this option is used, \f(CW\*(C`_\|_WORKAROUND_SPECULATIVE_SYNCS\*(C'\fR is defined.
.IP "\fB\-mno\-csync\-anomaly\fR" 4
.IX Item "-mno-csync-anomaly"
Don't generate extra code to prevent \s-1CSYNC\s0 or \s-1SSYNC\s0 instructions from
occurring too soon after a conditional branch.
.IP "\fB\-mlow\-64k\fR" 4
.IX Item "-mlow-64k"
When enabled, the compiler is free to take advantage of the knowledge that
the entire program fits into the low 64k of memory.
.IP "\fB\-mno\-low\-64k\fR" 4
.IX Item "-mno-low-64k"
Assume that the program is arbitrarily large.  This is the default.
.IP "\fB\-mstack\-check\-l1\fR" 4
.IX Item "-mstack-check-l1"
Do stack checking using information placed into L1 scratchpad memory by the
uClinux kernel.
.IP "\fB\-mid\-shared\-library\fR" 4
.IX Item "-mid-shared-library"
Generate code that supports shared libraries via the library \s-1ID\s0 method.
This allows for execute in place and shared libraries in an environment
without virtual memory management.  This option implies \fB\-fPIC\fR.
With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR.
.IP "\fB\-mno\-id\-shared\-library\fR" 4
.IX Item "-mno-id-shared-library"
Generate code that doesn't assume \s-1ID\s0 based shared libraries are being used.
This is the default.
.IP "\fB\-mleaf\-id\-shared\-library\fR" 4
.IX Item "-mleaf-id-shared-library"
Generate code that supports shared libraries via the library \s-1ID\s0 method,
but assumes that this library or executable won't link against any other
\&\s-1ID\s0 shared libraries.  That allows the compiler to use faster code for jumps
and calls.
.IP "\fB\-mno\-leaf\-id\-shared\-library\fR" 4
.IX Item "-mno-leaf-id-shared-library"
Do not assume that the code being compiled won't link against any \s-1ID\s0 shared
libraries.  Slower code will be generated for jump and call insns.
.IP "\fB\-mshared\-library\-id=n\fR" 4
.IX Item "-mshared-library-id=n"
Specified the identification number of the \s-1ID\s0 based shared library being
compiled.  Specifying a value of 0 will generate more compact code, specifying
other values will force the allocation of that number to the current
library but is no more space or time efficient than omitting this option.
.IP "\fB\-msep\-data\fR" 4
.IX Item "-msep-data"
Generate code that allows the data segment to be located in a different
area of memory from the text segment.  This allows for execute in place in
an environment without virtual memory management by eliminating relocations
against the text section.
.IP "\fB\-mno\-sep\-data\fR" 4
.IX Item "-mno-sep-data"
Generate code that assumes that the data segment follows the text segment.
This is the default.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
.PD 0
.IP "\fB\-mno\-long\-calls\fR" 4
.IX Item "-mno-long-calls"
.PD
Tells the compiler to perform function calls by first loading the
address of the function into a register and then performing a subroutine
call on this register.  This switch is needed if the target function
will lie outside of the 24 bit addressing range of the offset based
version of subroutine call instruction.
.Sp
This feature is not enabled by default.  Specifying
\&\fB\-mno\-long\-calls\fR will restore the default behavior.  Note these
switches have no effect on how the compiler generates code to handle
function calls via function pointers.
.IP "\fB\-mfast\-fp\fR" 4
.IX Item "-mfast-fp"
Link with the fast floating-point library. This library relaxes some of
the \s-1IEEE\s0 floating-point standard's rules for checking inputs against
Not-a-Number (\s-1NAN\s0), in the interest of performance.
.IP "\fB\-minline\-plt\fR" 4
.IX Item "-minline-plt"
Enable inlining of \s-1PLT\s0 entries in function calls to functions that are
not known to bind locally.  It has no effect without \fB\-mfdpic\fR.
.PP
\fI\s-1CRIS\s0 Options\fR
.IX Subsection "CRIS Options"
.PP
These options are defined specifically for the \s-1CRIS\s0 ports.
.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
.IX Item "-march=architecture-type"
.PD 0
.IP "\fB\-mcpu=\fR\fIarchitecture-type\fR" 4
.IX Item "-mcpu=architecture-type"
.PD
Generate code for the specified architecture.  The choices for
\&\fIarchitecture-type\fR are \fBv3\fR, \fBv8\fR and \fBv10\fR for
respectively \s-1ETRAX\s0\ 4, \s-1ETRAX\s0\ 100, and \s-1ETRAX\s0\ 100\ \s-1LX\s0.
Default is \fBv0\fR except for cris-axis-linux-gnu, where the default is
\&\fBv10\fR.
.IP "\fB\-mtune=\fR\fIarchitecture-type\fR" 4
.IX Item "-mtune=architecture-type"
Tune to \fIarchitecture-type\fR everything applicable about the generated
code, except for the \s-1ABI\s0 and the set of available instructions.  The
choices for \fIarchitecture-type\fR are the same as for
\&\fB\-march=\fR\fIarchitecture-type\fR.
.IP "\fB\-mmax\-stack\-frame=\fR\fIn\fR" 4
.IX Item "-mmax-stack-frame=n"
Warn when the stack frame of a function exceeds \fIn\fR bytes.
.IP "\fB\-melinux\-stacksize=\fR\fIn\fR" 4
.IX Item "-melinux-stacksize=n"
Only available with the \fBcris-axis-aout\fR target.  Arranges for
indications in the program to the kernel loader that the stack of the
program should be set to \fIn\fR bytes.
.IP "\fB\-metrax4\fR" 4
.IX Item "-metrax4"
.PD 0
.IP "\fB\-metrax100\fR" 4
.IX Item "-metrax100"
.PD
The options \fB\-metrax4\fR and \fB\-metrax100\fR are synonyms for
\&\fB\-march=v3\fR and \fB\-march=v8\fR respectively.
.IP "\fB\-mmul\-bug\-workaround\fR" 4
.IX Item "-mmul-bug-workaround"
.PD 0
.IP "\fB\-mno\-mul\-bug\-workaround\fR" 4
.IX Item "-mno-mul-bug-workaround"
.PD
Work around a bug in the \f(CW\*(C`muls\*(C'\fR and \f(CW\*(C`mulu\*(C'\fR instructions for \s-1CPU\s0
models where it applies.  This option is active by default.
.IP "\fB\-mpdebug\fR" 4
.IX Item "-mpdebug"
Enable CRIS-specific verbose debug-related information in the assembly
code.  This option also has the effect to turn off the \fB#NO_APP\fR
formatted-code indicator to the assembler at the beginning of the
assembly file.
.IP "\fB\-mcc\-init\fR" 4
.IX Item "-mcc-init"
Do not use condition-code results from previous instruction; always emit
compare and test instructions before use of condition codes.
.IP "\fB\-mno\-side\-effects\fR" 4
.IX Item "-mno-side-effects"
Do not emit instructions with side-effects in addressing modes other than
post-increment.
.IP "\fB\-mstack\-align\fR" 4
.IX Item "-mstack-align"
.PD 0
.IP "\fB\-mno\-stack\-align\fR" 4
.IX Item "-mno-stack-align"
.IP "\fB\-mdata\-align\fR" 4
.IX Item "-mdata-align"
.IP "\fB\-mno\-data\-align\fR" 4
.IX Item "-mno-data-align"
.IP "\fB\-mconst\-align\fR" 4
.IX Item "-mconst-align"
.IP "\fB\-mno\-const\-align\fR" 4
.IX Item "-mno-const-align"
.PD
These options (no-options) arranges (eliminate arrangements) for the
stack-frame, individual data and constants to be aligned for the maximum
single data access size for the chosen \s-1CPU\s0 model.  The default is to
arrange for 32\-bit alignment.  \s-1ABI\s0 details such as structure layout are
not affected by these options.
.IP "\fB\-m32\-bit\fR" 4
.IX Item "-m32-bit"
.PD 0
.IP "\fB\-m16\-bit\fR" 4
.IX Item "-m16-bit"
.IP "\fB\-m8\-bit\fR" 4
.IX Item "-m8-bit"
.PD
Similar to the stack\- data\- and const-align options above, these options
arrange for stack-frame, writable data and constants to all be 32\-bit,
16\-bit or 8\-bit aligned.  The default is 32\-bit alignment.
.IP "\fB\-mno\-prologue\-epilogue\fR" 4
.IX Item "-mno-prologue-epilogue"
.PD 0
.IP "\fB\-mprologue\-epilogue\fR" 4
.IX Item "-mprologue-epilogue"
.PD
With \fB\-mno\-prologue\-epilogue\fR, the normal function prologue and
epilogue that sets up the stack-frame are omitted and no return
instructions or return sequences are generated in the code.  Use this
option only together with visual inspection of the compiled code: no
warnings or errors are generated when call-saved registers must be saved,
or storage for local variable needs to be allocated.
.IP "\fB\-mno\-gotplt\fR" 4
.IX Item "-mno-gotplt"
.PD 0
.IP "\fB\-mgotplt\fR" 4
.IX Item "-mgotplt"
.PD
With \fB\-fpic\fR and \fB\-fPIC\fR, don't generate (do generate)
instruction sequences that load addresses for functions from the \s-1PLT\s0 part
of the \s-1GOT\s0 rather than (traditional on other architectures) calls to the
\&\s-1PLT\s0.  The default is \fB\-mgotplt\fR.
.IP "\fB\-maout\fR" 4
.IX Item "-maout"
Legacy no-op option only recognized with the cris-axis-aout target.
.IP "\fB\-melf\fR" 4
.IX Item "-melf"
Legacy no-op option only recognized with the cris-axis-elf and
cris-axis-linux-gnu targets.
.IP "\fB\-melinux\fR" 4
.IX Item "-melinux"
Only recognized with the cris-axis-aout target, where it selects a
GNU/linux\-like multilib, include files and instruction set for
\&\fB\-march=v8\fR.
.IP "\fB\-mlinux\fR" 4
.IX Item "-mlinux"
Legacy no-op option only recognized with the cris-axis-linux-gnu target.
.IP "\fB\-sim\fR" 4
.IX Item "-sim"
This option, recognized for the cris-axis-aout and cris-axis-elf arranges
to link with input-output functions from a simulator library.  Code,
initialized data and zero-initialized data are allocated consecutively.
.IP "\fB\-sim2\fR" 4
.IX Item "-sim2"
Like \fB\-sim\fR, but pass linker options to locate initialized data at
0x40000000 and zero-initialized data at 0x80000000.
.PP
\fI\s-1CRX\s0 Options\fR
.IX Subsection "CRX Options"
.PP
These options are defined specifically for the \s-1CRX\s0 ports.
.IP "\fB\-mmac\fR" 4
.IX Item "-mmac"
Enable the use of multiply-accumulate instructions. Disabled by default.
.IP "\fB\-mpush\-args\fR" 4
.IX Item "-mpush-args"
Push instructions will be used to pass outgoing arguments when functions
are called. Enabled by default.
.PP
\fIDarwin Options\fR
.IX Subsection "Darwin Options"
.PP
These options are defined for all architectures running the Darwin operating
system.
.PP
\&\s-1FSF\s0 \s-1GCC\s0 on Darwin does not create \*(L"fat\*(R" object files; it will create
an object file for the single architecture that it was built to
target.  Apple's \s-1GCC\s0 on Darwin does create \*(L"fat\*(R" files if multiple
\&\fB\-arch\fR options are used; it does so by running the compiler or
linker multiple times and joining the results together with
\&\fIlipo\fR.
.PP
The subtype of the file created (like \fBppc7400\fR or \fBppc970\fR or
\&\fBi686\fR) is determined by the flags that specify the \s-1ISA\s0
that \s-1GCC\s0 is targetting, like \fB\-mcpu\fR or \fB\-march\fR.  The
\&\fB\-force_cpusubtype_ALL\fR option can be used to override this.
.PP
The Darwin tools vary in their behavior when presented with an \s-1ISA\s0
mismatch.  The assembler, \fIas\fR, will only permit instructions to
be used that are valid for the subtype of the file it is generating,
so you cannot put 64\-bit instructions in an \fBppc750\fR object file.
The linker for shared libraries, \fI/usr/bin/libtool\fR, will fail
and print an error if asked to create a shared library with a less
restrictive subtype than its input files (for instance, trying to put
a \fBppc970\fR object file in a \fBppc7400\fR library).  The linker
for executables, \fIld\fR, will quietly give the executable the most
restrictive subtype of any of its input files.
.IP "\fB\-F\fR\fIdir\fR" 4
.IX Item "-Fdir"
Add the framework directory \fIdir\fR to the head of the list of
directories to be searched for header files.  These directories are
interleaved with those specified by \fB\-I\fR options and are
scanned in a left-to-right order.
.Sp
A framework directory is a directory with frameworks in it.  A
framework is a directory with a \fB\*(L"Headers\*(R"\fR and/or
\&\fB\*(L"PrivateHeaders\*(R"\fR directory contained directly in it that ends
in \fB\*(L".framework\*(R"\fR.  The name of a framework is the name of this
directory excluding the \fB\*(L".framework\*(R"\fR.  Headers associated with
the framework are found in one of those two directories, with
\&\fB\*(L"Headers\*(R"\fR being searched first.  A subframework is a framework
directory that is in a framework's \fB\*(L"Frameworks\*(R"\fR directory.
Includes of subframework headers can only appear in a header of a
framework that contains the subframework, or in a sibling subframework
header.  Two subframeworks are siblings if they occur in the same
framework.  A subframework should not have the same name as a
framework, a warning will be issued if this is violated.  Currently a
subframework cannot have subframeworks, in the future, the mechanism
may be extended to support this.  The standard frameworks can be found
in \fB\*(L"/System/Library/Frameworks\*(R"\fR and
\&\fB\*(L"/Library/Frameworks\*(R"\fR.  An example include looks like
\&\f(CW\*(C`#include <Framework/header.h>\*(C'\fR, where \fBFramework\fR denotes
the name of the framework and header.h is found in the
\&\fB\*(L"PrivateHeaders\*(R"\fR or \fB\*(L"Headers\*(R"\fR directory.
.IP "\fB\-iframework\fR\fIdir\fR" 4
.IX Item "-iframeworkdir"
Like \fB\-F\fR except the directory is a treated as a system
directory.  The main difference between this \fB\-iframework\fR and
\&\fB\-F\fR is that with \fB\-iframework\fR the compiler does not
warn about constructs contained within header files found via
\&\fIdir\fR.  This option is valid only for the C family of languages.
.IP "\fB\-gused\fR" 4
.IX Item "-gused"
Emit debugging information for symbols that are used.  For \s-1STABS\s0
debugging format, this enables \fB\-feliminate\-unused\-debug\-symbols\fR.
This is by default \s-1ON\s0.
.IP "\fB\-gfull\fR" 4
.IX Item "-gfull"
Emit debugging information for all symbols and types.
.IP "\fB\-mmacosx\-version\-min=\fR\fIversion\fR" 4
.IX Item "-mmacosx-version-min=version"
The earliest version of MacOS X that this executable will run on
is \fIversion\fR.  Typical values of \fIversion\fR include \f(CW10.1\fR,
\&\f(CW10.2\fR, and \f(CW10.3.9\fR.
.Sp
If the compiler was built to use the system's headers by default,
then the default for this option is the system version on which the
compiler is running, otherwise the default is to make choices which
are compatible with as many systems and code bases as possible.
.IP "\fB\-mkernel\fR" 4
.IX Item "-mkernel"
Enable kernel development mode.  The \fB\-mkernel\fR option sets
\&\fB\-static\fR, \fB\-fno\-common\fR, \fB\-fno\-cxa\-atexit\fR,
\&\fB\-fno\-exceptions\fR, \fB\-fno\-non\-call\-exceptions\fR,
\&\fB\-fapple\-kext\fR, \fB\-fno\-weak\fR and \fB\-fno\-rtti\fR where
applicable.  This mode also sets \fB\-mno\-altivec\fR,
\&\fB\-msoft\-float\fR, \fB\-fno\-builtin\fR and
\&\fB\-mlong\-branch\fR for PowerPC targets.
.IP "\fB\-mone\-byte\-bool\fR" 4
.IX Item "-mone-byte-bool"
Override the defaults for \fBbool\fR so that \fBsizeof(bool)==1\fR.
By default \fBsizeof(bool)\fR is \fB4\fR when compiling for
Darwin/PowerPC and \fB1\fR when compiling for Darwin/x86, so this
option has no effect on x86.
.Sp
\&\fBWarning:\fR The \fB\-mone\-byte\-bool\fR switch causes \s-1GCC\s0
to generate code that is not binary compatible with code generated
without that switch.  Using this switch may require recompiling all
other modules in a program, including system libraries.  Use this
switch to conform to a non-default data model.
.IP "\fB\-mfix\-and\-continue\fR" 4
.IX Item "-mfix-and-continue"
.PD 0
.IP "\fB\-ffix\-and\-continue\fR" 4
.IX Item "-ffix-and-continue"
.IP "\fB\-findirect\-data\fR" 4
.IX Item "-findirect-data"
.PD
Generate code suitable for fast turn around development.  Needed to
enable gdb to dynamically load \f(CW\*(C`.o\*(C'\fR files into already running
programs.  \fB\-findirect\-data\fR and \fB\-ffix\-and\-continue\fR
are provided for backwards compatibility.
.IP "\fB\-all_load\fR" 4
.IX Item "-all_load"
Loads all members of static archive libraries.
See man \fIld\fR\|(1) for more information.
.IP "\fB\-arch_errors_fatal\fR" 4
.IX Item "-arch_errors_fatal"
Cause the errors having to do with files that have the wrong architecture
to be fatal.
.IP "\fB\-bind_at_load\fR" 4
.IX Item "-bind_at_load"
Causes the output file to be marked such that the dynamic linker will
bind all undefined references when the file is loaded or launched.
.IP "\fB\-bundle\fR" 4
.IX Item "-bundle"
Produce a Mach-o bundle format file.
See man \fIld\fR\|(1) for more information.
.IP "\fB\-bundle_loader\fR \fIexecutable\fR" 4
.IX Item "-bundle_loader executable"
This option specifies the \fIexecutable\fR that will be loading the build
output file being linked.  See man \fIld\fR\|(1) for more information.
.IP "\fB\-dynamiclib\fR" 4
.IX Item "-dynamiclib"
When passed this option, \s-1GCC\s0 will produce a dynamic library instead of
an executable when linking, using the Darwin \fIlibtool\fR command.
.IP "\fB\-force_cpusubtype_ALL\fR" 4
.IX Item "-force_cpusubtype_ALL"
This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of
one controlled by the \fB\-mcpu\fR or \fB\-march\fR option.
.IP "\fB\-allowable_client\fR  \fIclient_name\fR" 4
.IX Item "-allowable_client  client_name"
.PD 0
.IP "\fB\-client_name\fR" 4
.IX Item "-client_name"
.IP "\fB\-compatibility_version\fR" 4
.IX Item "-compatibility_version"
.IP "\fB\-current_version\fR" 4
.IX Item "-current_version"
.IP "\fB\-dead_strip\fR" 4
.IX Item "-dead_strip"
.IP "\fB\-dependency\-file\fR" 4
.IX Item "-dependency-file"
.IP "\fB\-dylib_file\fR" 4
.IX Item "-dylib_file"
.IP "\fB\-dylinker_install_name\fR" 4
.IX Item "-dylinker_install_name"
.IP "\fB\-dynamic\fR" 4
.IX Item "-dynamic"
.IP "\fB\-exported_symbols_list\fR" 4
.IX Item "-exported_symbols_list"
.IP "\fB\-filelist\fR" 4
.IX Item "-filelist"
.IP "\fB\-flat_namespace\fR" 4
.IX Item "-flat_namespace"
.IP "\fB\-force_flat_namespace\fR" 4
.IX Item "-force_flat_namespace"
.IP "\fB\-headerpad_max_install_names\fR" 4
.IX Item "-headerpad_max_install_names"
.IP "\fB\-image_base\fR" 4
.IX Item "-image_base"
.IP "\fB\-init\fR" 4
.IX Item "-init"
.IP "\fB\-install_name\fR" 4
.IX Item "-install_name"
.IP "\fB\-keep_private_externs\fR" 4
.IX Item "-keep_private_externs"
.IP "\fB\-multi_module\fR" 4
.IX Item "-multi_module"
.IP "\fB\-multiply_defined\fR" 4
.IX Item "-multiply_defined"
.IP "\fB\-multiply_defined_unused\fR" 4
.IX Item "-multiply_defined_unused"
.IP "\fB\-noall_load\fR" 4
.IX Item "-noall_load"
.IP "\fB\-no_dead_strip_inits_and_terms\fR" 4
.IX Item "-no_dead_strip_inits_and_terms"
.IP "\fB\-nofixprebinding\fR" 4
.IX Item "-nofixprebinding"
.IP "\fB\-nomultidefs\fR" 4
.IX Item "-nomultidefs"
.IP "\fB\-noprebind\fR" 4
.IX Item "-noprebind"
.IP "\fB\-noseglinkedit\fR" 4
.IX Item "-noseglinkedit"
.IP "\fB\-pagezero_size\fR" 4
.IX Item "-pagezero_size"
.IP "\fB\-prebind\fR" 4
.IX Item "-prebind"
.IP "\fB\-prebind_all_twolevel_modules\fR" 4
.IX Item "-prebind_all_twolevel_modules"
.IP "\fB\-private_bundle\fR" 4
.IX Item "-private_bundle"
.IP "\fB\-read_only_relocs\fR" 4
.IX Item "-read_only_relocs"
.IP "\fB\-sectalign\fR" 4
.IX Item "-sectalign"
.IP "\fB\-sectobjectsymbols\fR" 4
.IX Item "-sectobjectsymbols"
.IP "\fB\-whyload\fR" 4
.IX Item "-whyload"
.IP "\fB\-seg1addr\fR" 4
.IX Item "-seg1addr"
.IP "\fB\-sectcreate\fR" 4
.IX Item "-sectcreate"
.IP "\fB\-sectobjectsymbols\fR" 4
.IX Item "-sectobjectsymbols"
.IP "\fB\-sectorder\fR" 4
.IX Item "-sectorder"
.IP "\fB\-segaddr\fR" 4
.IX Item "-segaddr"
.IP "\fB\-segs_read_only_addr\fR" 4
.IX Item "-segs_read_only_addr"
.IP "\fB\-segs_read_write_addr\fR" 4
.IX Item "-segs_read_write_addr"
.IP "\fB\-seg_addr_table\fR" 4
.IX Item "-seg_addr_table"
.IP "\fB\-seg_addr_table_filename\fR" 4
.IX Item "-seg_addr_table_filename"
.IP "\fB\-seglinkedit\fR" 4
.IX Item "-seglinkedit"
.IP "\fB\-segprot\fR" 4
.IX Item "-segprot"
.IP "\fB\-segs_read_only_addr\fR" 4
.IX Item "-segs_read_only_addr"
.IP "\fB\-segs_read_write_addr\fR" 4
.IX Item "-segs_read_write_addr"
.IP "\fB\-single_module\fR" 4
.IX Item "-single_module"
.IP "\fB\-static\fR" 4
.IX Item "-static"
.IP "\fB\-sub_library\fR" 4
.IX Item "-sub_library"
.IP "\fB\-sub_umbrella\fR" 4
.IX Item "-sub_umbrella"
.IP "\fB\-twolevel_namespace\fR" 4
.IX Item "-twolevel_namespace"
.IP "\fB\-umbrella\fR" 4
.IX Item "-umbrella"
.IP "\fB\-undefined\fR" 4
.IX Item "-undefined"
.IP "\fB\-unexported_symbols_list\fR" 4
.IX Item "-unexported_symbols_list"
.IP "\fB\-weak_reference_mismatches\fR" 4
.IX Item "-weak_reference_mismatches"
.IP "\fB\-whatsloaded\fR" 4
.IX Item "-whatsloaded"
.PD
These options are passed to the Darwin linker.  The Darwin linker man page
describes them in detail.
.PP
\fI\s-1DEC\s0 Alpha Options\fR
.IX Subsection "DEC Alpha Options"
.PP
These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha implementations:
.IP "\fB\-mno\-soft\-float\fR" 4
.IX Item "-mno-soft-float"
.PD 0
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
.PD
Use (do not use) the hardware floating-point instructions for
floating-point operations.  When \fB\-msoft\-float\fR is specified,
functions in \fIlibgcc.a\fR will be used to perform floating-point
operations.  Unless they are replaced by routines that emulate the
floating-point operations, or compiled in such a way as to call such
emulations routines, these routines will issue floating-point
operations.   If you are compiling for an Alpha without floating-point
operations, you must ensure that the library is built so as not to call
them.
.Sp
Note that Alpha implementations without floating-point operations are
required to have floating-point registers.
.IP "\fB\-mfp\-reg\fR" 4
.IX Item "-mfp-reg"
.PD 0
.IP "\fB\-mno\-fp\-regs\fR" 4
.IX Item "-mno-fp-regs"
.PD
Generate code that uses (does not use) the floating-point register set.
\&\fB\-mno\-fp\-regs\fR implies \fB\-msoft\-float\fR.  If the floating-point
register set is not used, floating point operands are passed in integer
registers as if they were integers and floating-point results are passed
in \f(CW$0\fR instead of \f(CW$f0\fR.  This is a non-standard calling sequence,
so any function with a floating-point argument or return value called by code
compiled with \fB\-mno\-fp\-regs\fR must also be compiled with that
option.
.Sp
A typical use of this option is building a kernel that does not use,
and hence need not save and restore, any floating-point registers.
.IP "\fB\-mieee\fR" 4
.IX Item "-mieee"
The Alpha architecture implements floating-point hardware optimized for
maximum performance.  It is mostly compliant with the \s-1IEEE\s0 floating
point standard.  However, for full compliance, software assistance is
required.  This option generates code fully \s-1IEEE\s0 compliant code
\&\fIexcept\fR that the \fIinexact-flag\fR is not maintained (see below).
If this option is turned on, the preprocessor macro \f(CW\*(C`_IEEE_FP\*(C'\fR is
defined during compilation.  The resulting code is less efficient but is
able to correctly support denormalized numbers and exceptional \s-1IEEE\s0
values such as not-a-number and plus/minus infinity.  Other Alpha
compilers call this option \fB\-ieee_with_no_inexact\fR.
.IP "\fB\-mieee\-with\-inexact\fR" 4
.IX Item "-mieee-with-inexact"
This is like \fB\-mieee\fR except the generated code also maintains
the \s-1IEEE\s0 \fIinexact-flag\fR.  Turning on this option causes the
generated code to implement fully-compliant \s-1IEEE\s0 math.  In addition to
\&\f(CW\*(C`_IEEE_FP\*(C'\fR, \f(CW\*(C`_IEEE_FP_EXACT\*(C'\fR is defined as a preprocessor
macro.  On some Alpha implementations the resulting code may execute
significantly slower than the code generated by default.  Since there is
very little code that depends on the \fIinexact-flag\fR, you should
normally not specify this option.  Other Alpha compilers call this
option \fB\-ieee_with_inexact\fR.
.IP "\fB\-mfp\-trap\-mode=\fR\fItrap-mode\fR" 4
.IX Item "-mfp-trap-mode=trap-mode"
This option controls what floating-point related traps are enabled.
Other Alpha compilers call this option \fB\-fptm\fR \fItrap-mode\fR.
The trap mode can be set to one of four values:
.RS 4
.IP "\fBn\fR" 4
.IX Item "n"
This is the default (normal) setting.  The only traps that are enabled
are the ones that cannot be disabled in software (e.g., division by zero
trap).
.IP "\fBu\fR" 4
.IX Item "u"
In addition to the traps enabled by \fBn\fR, underflow traps are enabled
as well.
.IP "\fBsu\fR" 4
.IX Item "su"
Like \fBu\fR, but the instructions are marked to be safe for software
completion (see Alpha architecture manual for details).
.IP "\fBsui\fR" 4
.IX Item "sui"
Like \fBsu\fR, but inexact traps are enabled as well.
.RE
.RS 4
.RE
.IP "\fB\-mfp\-rounding\-mode=\fR\fIrounding-mode\fR" 4
.IX Item "-mfp-rounding-mode=rounding-mode"
Selects the \s-1IEEE\s0 rounding mode.  Other Alpha compilers call this option
\&\fB\-fprm\fR \fIrounding-mode\fR.  The \fIrounding-mode\fR can be one
of:
.RS 4
.IP "\fBn\fR" 4
.IX Item "n"
Normal \s-1IEEE\s0 rounding mode.  Floating point numbers are rounded towards
the nearest machine number or towards the even machine number in case
of a tie.
.IP "\fBm\fR" 4
.IX Item "m"
Round towards minus infinity.
.IP "\fBc\fR" 4
.IX Item "c"
Chopped rounding mode.  Floating point numbers are rounded towards zero.
.IP "\fBd\fR" 4
.IX Item "d"
Dynamic rounding mode.  A field in the floating point control register
(\fIfpcr\fR, see Alpha architecture reference manual) controls the
rounding mode in effect.  The C library initializes this register for
rounding towards plus infinity.  Thus, unless your program modifies the
\&\fIfpcr\fR, \fBd\fR corresponds to round towards plus infinity.
.RE
.RS 4
.RE
.IP "\fB\-mtrap\-precision=\fR\fItrap-precision\fR" 4
.IX Item "-mtrap-precision=trap-precision"
In the Alpha architecture, floating point traps are imprecise.  This
means without software assistance it is impossible to recover from a
floating trap and program execution normally needs to be terminated.
\&\s-1GCC\s0 can generate code that can assist operating system trap handlers
in determining the exact location that caused a floating point trap.
Depending on the requirements of an application, different levels of
precisions can be selected:
.RS 4
.IP "\fBp\fR" 4
.IX Item "p"
Program precision.  This option is the default and means a trap handler
can only identify which program caused a floating point exception.
.IP "\fBf\fR" 4
.IX Item "f"
Function precision.  The trap handler can determine the function that
caused a floating point exception.
.IP "\fBi\fR" 4
.IX Item "i"
Instruction precision.  The trap handler can determine the exact
instruction that caused a floating point exception.
.RE
.RS 4
.Sp
Other Alpha compilers provide the equivalent options called
\&\fB\-scope_safe\fR and \fB\-resumption_safe\fR.
.RE
.IP "\fB\-mieee\-conformant\fR" 4
.IX Item "-mieee-conformant"
This option marks the generated code as \s-1IEEE\s0 conformant.  You must not
use this option unless you also specify \fB\-mtrap\-precision=i\fR and either
\&\fB\-mfp\-trap\-mode=su\fR or \fB\-mfp\-trap\-mode=sui\fR.  Its only effect
is to emit the line \fB.eflag 48\fR in the function prologue of the
generated assembly file.  Under \s-1DEC\s0 Unix, this has the effect that
IEEE-conformant math library routines will be linked in.
.IP "\fB\-mbuild\-constants\fR" 4
.IX Item "-mbuild-constants"
Normally \s-1GCC\s0 examines a 32\- or 64\-bit integer constant to
see if it can construct it from smaller constants in two or three
instructions.  If it cannot, it will output the constant as a literal and
generate code to load it from the data segment at runtime.
.Sp
Use this option to require \s-1GCC\s0 to construct \fIall\fR integer constants
using code, even if it takes more instructions (the maximum is six).
.Sp
You would typically use this option to build a shared library dynamic
loader.  Itself a shared library, it must relocate itself in memory
before it can find the variables and constants in its own data segment.
.IP "\fB\-malpha\-as\fR" 4
.IX Item "-malpha-as"
.PD 0
.IP "\fB\-mgas\fR" 4
.IX Item "-mgas"
.PD
Select whether to generate code to be assembled by the vendor-supplied
assembler (\fB\-malpha\-as\fR) or by the \s-1GNU\s0 assembler \fB\-mgas\fR.
.IP "\fB\-mbwx\fR" 4
.IX Item "-mbwx"
.PD 0
.IP "\fB\-mno\-bwx\fR" 4
.IX Item "-mno-bwx"
.IP "\fB\-mcix\fR" 4
.IX Item "-mcix"
.IP "\fB\-mno\-cix\fR" 4
.IX Item "-mno-cix"
.IP "\fB\-mfix\fR" 4
.IX Item "-mfix"
.IP "\fB\-mno\-fix\fR" 4
.IX Item "-mno-fix"
.IP "\fB\-mmax\fR" 4
.IX Item "-mmax"
.IP "\fB\-mno\-max\fR" 4
.IX Item "-mno-max"
.PD
Indicate whether \s-1GCC\s0 should generate code to use the optional \s-1BWX\s0,
\&\s-1CIX\s0, \s-1FIX\s0 and \s-1MAX\s0 instruction sets.  The default is to use the instruction
sets supported by the \s-1CPU\s0 type specified via \fB\-mcpu=\fR option or that
of the \s-1CPU\s0 on which \s-1GCC\s0 was built if none was specified.
.IP "\fB\-mfloat\-vax\fR" 4
.IX Item "-mfloat-vax"
.PD 0
.IP "\fB\-mfloat\-ieee\fR" 4
.IX Item "-mfloat-ieee"
.PD
Generate code that uses (does not use) \s-1VAX\s0 F and G floating point
arithmetic instead of \s-1IEEE\s0 single and double precision.
.IP "\fB\-mexplicit\-relocs\fR" 4
.IX Item "-mexplicit-relocs"
.PD 0
.IP "\fB\-mno\-explicit\-relocs\fR" 4
.IX Item "-mno-explicit-relocs"
.PD
Older Alpha assemblers provided no way to generate symbol relocations
except via assembler macros.  Use of these macros does not allow
optimal instruction scheduling.  \s-1GNU\s0 binutils as of version 2.12
supports a new syntax that allows the compiler to explicitly mark
which relocations should apply to which instructions.  This option
is mostly useful for debugging, as \s-1GCC\s0 detects the capabilities of
the assembler when it is built and sets the default accordingly.
.IP "\fB\-msmall\-data\fR" 4
.IX Item "-msmall-data"
.PD 0
.IP "\fB\-mlarge\-data\fR" 4
.IX Item "-mlarge-data"
.PD
When \fB\-mexplicit\-relocs\fR is in effect, static data is
accessed via \fIgp-relative\fR relocations.  When \fB\-msmall\-data\fR
is used, objects 8 bytes long or smaller are placed in a \fIsmall data area\fR
(the \f(CW\*(C`.sdata\*(C'\fR and \f(CW\*(C`.sbss\*(C'\fR sections) and are accessed via
16\-bit relocations off of the \f(CW$gp\fR register.  This limits the
size of the small data area to 64KB, but allows the variables to be
directly accessed via a single instruction.
.Sp
The default is \fB\-mlarge\-data\fR.  With this option the data area
is limited to just below 2GB.  Programs that require more than 2GB of
data must use \f(CW\*(C`malloc\*(C'\fR or \f(CW\*(C`mmap\*(C'\fR to allocate the data in the
heap instead of in the program's data segment.
.Sp
When generating code for shared libraries, \fB\-fpic\fR implies
\&\fB\-msmall\-data\fR and \fB\-fPIC\fR implies \fB\-mlarge\-data\fR.
.IP "\fB\-msmall\-text\fR" 4
.IX Item "-msmall-text"
.PD 0
.IP "\fB\-mlarge\-text\fR" 4
.IX Item "-mlarge-text"
.PD
When \fB\-msmall\-text\fR is used, the compiler assumes that the
code of the entire program (or shared library) fits in 4MB, and is
thus reachable with a branch instruction.  When \fB\-msmall\-data\fR
is used, the compiler can assume that all local symbols share the
same \f(CW$gp\fR value, and thus reduce the number of instructions
required for a function call from 4 to 1.
.Sp
The default is \fB\-mlarge\-text\fR.
.IP "\fB\-mcpu=\fR\fIcpu_type\fR" 4
.IX Item "-mcpu=cpu_type"
Set the instruction set and instruction scheduling parameters for
machine type \fIcpu_type\fR.  You can specify either the \fB\s-1EV\s0\fR
style name or the corresponding chip number.  \s-1GCC\s0 supports scheduling
parameters for the \s-1EV4\s0, \s-1EV5\s0 and \s-1EV6\s0 family of processors and will
choose the default values for the instruction set from the processor
you specify.  If you do not specify a processor type, \s-1GCC\s0 will default
to the processor on which the compiler was built.
.Sp
Supported values for \fIcpu_type\fR are
.RS 4
.IP "\fBev4\fR" 4
.IX Item "ev4"
.PD 0
.IP "\fBev45\fR" 4
.IX Item "ev45"
.IP "\fB21064\fR" 4
.IX Item "21064"
.PD
Schedules as an \s-1EV4\s0 and has no instruction set extensions.
.IP "\fBev5\fR" 4
.IX Item "ev5"
.PD 0
.IP "\fB21164\fR" 4
.IX Item "21164"
.PD
Schedules as an \s-1EV5\s0 and has no instruction set extensions.
.IP "\fBev56\fR" 4
.IX Item "ev56"
.PD 0
.IP "\fB21164a\fR" 4
.IX Item "21164a"
.PD
Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 extension.
.IP "\fBpca56\fR" 4
.IX Item "pca56"
.PD 0
.IP "\fB21164pc\fR" 4
.IX Item "21164pc"
.IP "\fB21164PC\fR" 4
.IX Item "21164PC"
.PD
Schedules as an \s-1EV5\s0 and supports the \s-1BWX\s0 and \s-1MAX\s0 extensions.
.IP "\fBev6\fR" 4
.IX Item "ev6"
.PD 0
.IP "\fB21264\fR" 4
.IX Item "21264"
.PD
Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
.IP "\fBev67\fR" 4
.IX Item "ev67"
.PD 0
.IP "\fB21264a\fR" 4
.IX Item "21264a"
.PD
Schedules as an \s-1EV6\s0 and supports the \s-1BWX\s0, \s-1CIX\s0, \s-1FIX\s0, and \s-1MAX\s0 extensions.
.RE
.RS 4
.RE
.IP "\fB\-mtune=\fR\fIcpu_type\fR" 4
.IX Item "-mtune=cpu_type"
Set only the instruction scheduling parameters for machine type
\&\fIcpu_type\fR.  The instruction set is not changed.
.IP "\fB\-mmemory\-latency=\fR\fItime\fR" 4
.IX Item "-mmemory-latency=time"
Sets the latency the scheduler should assume for typical memory
references as seen by the application.  This number is highly
dependent on the memory access patterns used by the application
and the size of the external cache on the machine.
.Sp
Valid options for \fItime\fR are
.RS 4
.IP "\fInumber\fR" 4
.IX Item "number"
A decimal number representing clock cycles.
.IP "\fBL1\fR" 4
.IX Item "L1"
.PD 0
.IP "\fBL2\fR" 4
.IX Item "L2"
.IP "\fBL3\fR" 4
.IX Item "L3"
.IP "\fBmain\fR" 4
.IX Item "main"
.PD
The compiler contains estimates of the number of clock cycles for
\&\*(L"typical\*(R" \s-1EV4\s0 & \s-1EV5\s0 hardware for the Level 1, 2 & 3 caches
(also called Dcache, Scache, and Bcache), as well as to main memory.
Note that L3 is only valid for \s-1EV5\s0.
.RE
.RS 4
.RE
.PP
\fI\s-1DEC\s0 Alpha/VMS Options\fR
.IX Subsection "DEC Alpha/VMS Options"
.PP
These \fB\-m\fR options are defined for the \s-1DEC\s0 Alpha/VMS implementations:
.IP "\fB\-mvms\-return\-codes\fR" 4
.IX Item "-mvms-return-codes"
Return \s-1VMS\s0 condition codes from main.  The default is to return \s-1POSIX\s0
style condition (e.g. error) codes.
.PP
\fI\s-1FRV\s0 Options\fR
.IX Subsection "FRV Options"
.IP "\fB\-mgpr\-32\fR" 4
.IX Item "-mgpr-32"
Only use the first 32 general purpose registers.
.IP "\fB\-mgpr\-64\fR" 4
.IX Item "-mgpr-64"
Use all 64 general purpose registers.
.IP "\fB\-mfpr\-32\fR" 4
.IX Item "-mfpr-32"
Use only the first 32 floating point registers.
.IP "\fB\-mfpr\-64\fR" 4
.IX Item "-mfpr-64"
Use all 64 floating point registers
.IP "\fB\-mhard\-float\fR" 4
.IX Item "-mhard-float"
Use hardware instructions for floating point operations.
.IP "\fB\-msoft\-float\fR" 4
.IX Item "-msoft-float"
Use library routines for floating point operations.
.IP "\fB\-malloc\-cc\fR" 4
.IX Item "-malloc-cc"
Dynamically allocate condition code registers.
.IP "\fB\-mfixed\-cc\fR" 4
.IX Item "-mfixed-cc"
Do not try to dynamically allocate condition code registers, only
use \f(CW\*(C`icc0\*(C'\fR and \f(CW\*(C`fcc0\*(C'\fR.
.IP "\fB\-mdword\fR" 4
.IX Item "-mdword"
Change \s-1ABI\s0 to use double word insns.
.IP "\fB\-mno\-dword\fR" 4
.IX Item "-mno-dword"
Do not use double word instructions.
.IP "\fB\-mdouble\fR" 4
.IX Item "-mdouble"
Use floating point double instructions.
.IP "\fB\-mno\-double\fR" 4
.IX Item "-mno-double"
Do not use floating point double instructions.
.IP "\fB\-mmedia\fR" 4
.IX Item "-mmedia"
Use media instructions.
.IP "\fB\-mno\-media\fR" 4
.IX Item "-mno-media"
Do not use media instructions.
.IP "\fB\-mmuladd\fR" 4
.IX Item "-mmuladd"
Use multiply and add/subtract instructions.
.IP "\fB\-mno\-muladd\fR" 4
.IX Item "-mno-muladd"
Do not use multiply and add/subtract instructions.
.IP "\fB\-mfdpic\fR" 4
.IX Item "-mfdpic"
Select the \s-1FDPIC\s0 \s-1ABI\s0, that uses function descriptors to represent
pointers to functions.  Without any PIC/PIE\-related options, it
implies \fB\-fPIE\fR.  With \fB\-fpic\fR or \fB\-fpie\fR, it
assumes \s-1GOT\s0 entries and small data are within a 12\-bit range from the
\&\s-1GOT\s0 base address; with \fB\-fPIC\fR or \fB\-fPIE\fR, \s-1GOT\s0 offsets
are computed with 32 bits.
With a \fBbfin-elf\fR target, this option implies \fB\-msim\fR.
.IP "\fB\-minline\-plt\fR" 4
.IX Item "-minline-plt"
Enable inlining of \s-1PLT\s0 entries in function calls to functions that are
not known to bind locally.  It has no effect without \fB\-mfdpic\fR.
It's enabled by default if optimizing for speed and compiling for
shared libraries (i.e., \fB\-fPIC\fR or \fB\-fpic\fR), or when an
optimization option such as \fB\-O3\fR or above is present in the
command line.
.IP "\fB\-mTLS\fR" 4
.IX Item "-mTLS"
Assume a large \s-1TLS\s0 segment when generating thread-local code.
.IP "\fB\-mtls\fR" 4
.IX Item "-mtls"
Do not assume a large \s-1TLS\s0 segment when generating thread-local code.
.IP "\fB\-mgprel\-ro\fR" 4
.IX Item "-mgprel-ro"
Enable the use of \f(CW\*(C`GPREL\*(C'\fR relocations in the \s-1FDPIC\s0 \s-1ABI\s0 for data
that is known to be in read-only sections.  It's enabled by default,
except for \fB\-fpic\fR or \fB\-fpie\fR: even though it may help
make the global offset table smaller, it trades 1 instruction for 4.
With \fB\-fPIC\fR or \fB\-fPIE\fR, it trades 3 instructions for 4,
one of which may be shared by multiple symbols, and it avoids the need
for a \s-1GOT\s0 entry for the referenced symbol, so it's more likely to be a
win.  If it is not, \fB\-mno\-gprel\-ro\fR can be used to disable it.
.IP "\fB\-multilib\-library\-pic\fR" 4
.IX Item "-multilib-library-pic"
Link with the (library, not \s-1FD\s0) pic libraries.  It's implied by
\&\fB\-mlibrary\-pic\fR, as well as by \fB\-fPIC\fR and
\&\fB\-fpic\fR without \fB\-mfdpic\fR.  You should never have to use
it explicitly.
.IP "\fB\-mlinked\-fp\fR" 4
.IX Item "-mlinked-fp"
Follow the \s-1EABI\s0 requirement of always creating a frame pointer whenever
a stack frame is allocated.  This option is enabled by default and can
be disabled with \fB\-mno\-linked\-fp\fR.
.IP "\fB\-mlong\-calls\fR" 4
.IX Item "-mlong-calls"
Use indirect addressing to call functions outside the current
compilation unit.  This allows the functions to be placed anywhere
within the 32\-bit address space.
.IP "\fB\-malign\-labels\fR" 4
.IX Item "-malign-labels"
Try to align labels to an 8\-byte boundary by inserting nops into the
previous packet.  This option only has an effect when \s-1VLIW\s0 packing
is enabled.  It doesn't create new packets; it merely adds nops to
existing ones.
.IP "\fB\-mlibrary\-pic\fR" 4
.IX Item "-mlibrary-pic"
Generate position-independent \s-1EABI\s0 code.
.IP "\fB\-macc\-4\fR" 4
.IX Item "-macc-4"
Use only the first four media accumulator registers.
.IP "\fB\-macc\-8\fR" 4
.IX Item "-macc-8"
Use all eight media accumulator registers.
.IP "\fB\-mpack\fR" 4
.IX Item "-mpack"
Pack \s-1VLIW\s0 instructions.
.IP "\fB\-mno\-pack\fR" 4
.IX Item "-mno-pack"
Do not pack \s-1VLIW\s0 instructions.
.IP "\fB\-mno\-eflags\fR" 4
.IX Item "-mno-eflags"
Do not mark \s-1ABI\s0 switches in e_flags.
.IP "\fB\-mcond\-move\fR" 4
.IX Item "-mcond-move"
Enable the use of conditional-move instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-cond\-move\fR" 4
.IX Item "-mno-cond-move"
Disable the use of conditional-move instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mscc\fR" 4
.IX Item "-mscc"
Enable the use of conditional set instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-scc\fR" 4
.IX Item "-mno-scc"
Disable the use of conditional set instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mcond\-exec\fR" 4
.IX Item "-mcond-exec"
Enable the use of conditional execution (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-cond\-exec\fR" 4
.IX Item "-mno-cond-exec"
Disable the use of conditional execution.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mvliw\-branch\fR" 4
.IX Item "-mvliw-branch"
Run a pass to pack branches into \s-1VLIW\s0 instructions (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-vliw\-branch\fR" 4
.IX Item "-mno-vliw-branch"
Do not run a pass to pack branches into \s-1VLIW\s0 instructions.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mmulti\-cond\-exec\fR" 4
.IX Item "-mmulti-cond-exec"
Enable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution
(default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-multi\-cond\-exec\fR" 4
.IX Item "-mno-multi-cond-exec"
Disable optimization of \f(CW\*(C`&&\*(C'\fR and \f(CW\*(C`||\*(C'\fR in conditional execution.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mnested\-cond\-exec\fR" 4
.IX Item "-mnested-cond-exec"
Enable nested conditional execution optimizations (default).
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-mno\-nested\-cond\-exec\fR" 4
.IX Item "-mno-nested-cond-exec"
Disable nested conditional execution optimizations.
.Sp
This switch is mainly for debugging the compiler and will likely be removed
in a future version.
.IP "\fB\-moptimize\-membar\fR" 4
.IX Item "-moptimize-membar"
This switch removes redundant \f(CW\*(C`membar\*(C'\fR instructions from the
compiler generated code.  It is enabled by default.
.IP "\fB\-mno\-optimize\-membar\fR" 4
.IX Item "-mno-optimize-membar"
This switch disables the automatic removal of redundant \f(CW\*(C`membar\*(C'\fR
instructions from the generated code.
.IP "\fB\-mtomcat\-stats\fR" 4
.IX Item "-mtomcat-stats"
Cause gas to print out tomcat statistics.
.IP "\fB\-mcpu=\fR\fIcpu\fR" 4
.IX Item "-mcpu=cpu"
Select the processor type for which to generate code.  Possible values are
\&\fBfrv\fR, \fBfr550\fR, \fBtomcat\fR, \fBfr500\fR, \fBfr450\fR,
\&\fBfr405\fR, \fBfr400\fR, \fBfr300\fR and \fBsimple\fR.
.PP
\fIGNU/Linux Options\fR
.IX Subsection "GNU/Linux Options"
.PP
These \fB\-m\fR options are defined for GNU/Linux targets:
.IP "\fB\-mglibc\fR" 4
.IX Item "-mglibc"
Use the \s-1GNU\s0 C library instead of uClibc.  This is the default except
on \fB*\-*\-linux\-*uclibc*\fR targets.
.IP "\fB\-muclibc\fR" 4
.IX Item "-muclibc"
Use uClibc instead of the \s-1GNU\s0 C library.  This is the default on
\&\fB*\-*\-linux\-*uclibc*\fR targets.
.PP
\fIH8/300 Options\fR
.IX Subsection "H8/300 Options"
.PP
These \fB\-m\fR options are defined for the H8/300 implementations:
.IP "\fB\-mrelax\fR" 4
.IX Item "-mrelax"
Shorten some address references at link time, when possible; uses the
linker option \fB\-relax\fR.
.IP "\fB\-mh\fR" 4
.IX Item "-mh"
Generate code for the H8/300H.
.IP "\fB\-ms\fR" 4
.IX Item "-ms"
Generate code for the H8S.
.IP "\fB\-mn\fR" 4
.IX Item "-mn"
Generate code for the H8S and H8/300H in the normal mode.  This switch
must be used either with \fB\-mh\fR or \fB\-ms\fR.
.IP "\fB\-ms2600\fR" 4
.IX Item "-ms2600"
Generate code for the H8S/2600.  This switch must be used with \fB\-ms\fR.
.IP "\fB\-mint32\fR" 4
.IX Item "-mint32"
Make \f(CW\*(C`int\*(C'\fR data 32 bits by default.
.IP "\fB\-malign\-300\fR" 4
.IX Item "-malign-300"
On the H8/300H and H8S, use the same alignment rules as for the H8/300.
The default for the H8/300H and H8S is to align longs and floats on 4
byte boundaries.
\&\fB\-malign\-300\fR causes them to be aligned on 2 byte boundaries.
This option has no effect on the H8/300.
.PP
\fI\s-1HPPA\s0 Options\fR
.IX Subsection "HPPA Options"
.PP
These \fB\-m\fR options are defined for the \s-1HPPA\s0 family of computers:
.IP "\fB\-march=\fR\fIarchitecture-type\fR" 4
.IX Item "-march=architecture-type"
Generate code for the specified architecture.  The choices for
\&\fIarchitecture-type\fR are \fB1.0\fR for \s-1PA\s0 1.0, \fB1.1\fR for \s-1PA\s0
1.1, and \fB2.0\fR for \s-1PA\s0 2.0 processors.  Refer to
\&\fI/usr/lib/sched.models\fR on an HP-UX system to determine the proper
architecture option for your machine.  Code compiled for lower numbered
architectures will run on higher numbered architectures, but not the
other way around.
.IP "\fB\-mpa\-risc\-1\-0\fR" 4
.IX Item "-mpa-risc-1-0"
.PD 0
.IP "\fB\-mpa\-risc\-1\-1\fR" 4
.IX Item "-mpa-risc-1-1"
.IP "\fB\-mpa\-risc\-2\-0\fR" 4
.IX Item "-mpa-risc-2-0"
.PD
Synonyms for \fB\-march=1.0\fR, \fB\-march=1.1\fR, and \fB\-march=2.0\fR respectively.
.IP "\fB\-mbig\-switch\fR" 4
.IX Item "-mbig-switch"
Generate code suitable for big switch tables.  Use this option only if
the assembler/linker complain about out of range branches within a switch
table.
.IP "\fB\-mjump\-in\-delay\fR" 4
.IX Item "-mjump-in-delay"
Fill delay slots of function calls with unconditional jump instructions
by modifying the return pointer for the function call to be the target
of the conditional jump.
.IP "\fB\-mdisable\-fpregs\fR" 4
.IX Item "-mdisable-fpregs"
Prevent floating point registers from being used in any manner.  This is
necessary for compiling kernels which perform lazy context switching of
floating point registers.  If you use this option and attempt to perform
floating point operations, the compiler will abort.
.IP "\fB\-mdisable\-indexing\fR" 4
.IX Item "-mdisable-indexing"
Prevent the compiler from using indexing address modes.  This avoids some
rather obscure problems when compiling \s-1MIG\s0 generated code under \s-1MACH\s0.
.IP "\fB\-mno\-space\-regs\fR" 4
.IX Item "-mno-space-regs"
Generate code that assumes the target has no space registers.  This allows
\&\s-1GCC\s0 to generate faster indirect calls and use unscaled index address modes.
.Sp
Such code is suitable for level 0 \s-1PA\s0 systems and kernels.
.IP "\fB\-mfast\-indirect\-calls\fR" 4
.IX Item "-mfast-indirect-calls"
Generate code that assumes calls never cross space boundaries.  This
allows \s-1GCC\s0 to emit code which performs faster indirect calls.
.Sp
This option will not work in the presence of shared libraries or nested
functions.
.IP "\fB\-mfixed\-range=\fR\fIregister-range\fR" 4
.IX Item "-mfixed-range=register-range"
Generate code treating the given register range as fixed registers.
A fixed register is one that the register allocator can not use.  This is
useful when compiling kernel code.  A register range is specified as
two registers separated by a dash.  Multiple register ranges can be
specified separated by a comma.
.IP "\fB\-mlong\-load\-store\fR" 4
.IX Item "-mlong-load-store"
Generate 3\-instruction load and store sequences as sometimes required by
the HP-UX 10 linker.  This is equivalent to the \fB+k\fR option to
the \s-1HP\s0 compilers.
.IP "\fB\-mportable\-runtime\fR" 4
.IX Item "-mportable-runtime"
Use the portable calling conventions proposed by \s-1HP\s0 for \s-1ELF\s0 systems.
.IP "\fB\-mgas\fR" 4
.IX Item "-mgas"
Enable the use of assembler directives only \s-1GAS\s0 understands.
.IP "\fB\-mschedule=\fR\fIcpu-type\fR" 4
.IX Item "-mschedule=cpu-type"
Schedule code according to the constraints for the machine type
\&\fIcpu-type\fR.  The choices for \fIcpu-type\fR are \fB700\fR
\&\fB7100\fR, \fB7100LC\fR, \fB7200\fR, \fB7300\fR and \fB8000\fR.  Refer
to \fI/usr/lib/sched.models\fR on an HP-UX system to determine the
proper scheduling option for your machine.  The default scheduling is
\&\fB8000\fR.
.IP "\fB\-mlinker\-opt\fR" 4
.IX Item "-mlinker-opt"
Enable the optimization pass in the HP-UX linker.  Note this makes symbolic
debugging impossible.  It also triggers a bug in the HP-UX 8