he instruction pairs they may expand into: Compare and Branch Jump Expanded to ------ ------ ------------ bbc chkbit; bno bbs chkbit; bo cmpibe cmpije cmpi; be cmpibg cmpijg cmpi; bg cmpibge cmpijge cmpi; bge cmpibl cmpijl cmpi; bl cmpible cmpijle cmpi; ble cmpibno cmpijno cmpi; bno cmpibne cmpijne cmpi; bne cmpibo cmpijo cmpi; bo cmpobe cmpoje cmpo; be cmpobg cmpojg cmpo; bg cmpobge cmpojge cmpo; bge cmpobl cmpojl cmpo; bl cmpoble cmpojle cmpo; ble cmpobne cmpojne cmpo; bne  File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies 9.16 IA-64 Dependent Features ============================= * Menu: * IA-64 Options:: Options * IA-64 Syntax:: Syntax * IA-64 Opcodes:: Opcodes  File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 9.16.1 Options -------------- `-mconstant-gp' This option instructs the assembler to mark the resulting object file as using the "constant GP" model. With this model, it is assumed that the entire program uses a single global pointer (GP) value. Note that this option does not in any fashion affect the machine code emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP flag in the ELF file header. `-mauto-pic' This option instructs the assembler to mark the resulting object file as using the "constant GP without function descriptor" data model. This model is like the "constant GP" model, except that it additionally does away with function descriptors. What this means is that the address of a function refers directly to the function's code entry-point. Normally, such an address would refer to a function descriptor, which contains both the code entry-point and the GP-value needed by the function. Note that this option does not in any fashion affect the machine code emitted by the assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. `-milp32' `-milp64' `-mlp64' `-mp64' These options select the data model. The assembler defaults to `-mlp64' (LP64 data model). `-mle' `-mbe' These options select the byte order. The `-mle' option selects little-endian byte order (default) and `-mbe' selects big-endian byte order. Note that IA-64 machine code always uses little-endian byte order. `-mtune=itanium1' `-mtune=itanium2' Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default is ITANIUM2. `-munwind-check=warning' `-munwind-check=error' These options control what the assembler will do when performing consistency checks on unwind directives. `-munwind-check=warning' will make the assembler issue a warning when an unwind directive check fails. This is the default. `-munwind-check=error' will make the assembler issue an error when an unwind directive check fails. `-mhint.b=ok' `-mhint.b=warning' `-mhint.b=error' These options control what the assembler will do when the `hint.b' instruction is used. `-mhint.b=ok' will make the assembler accept `hint.b'. `-mint.b=warning' will make the assembler issue a warning when `hint.b' is used. `-mhint.b=error' will make the assembler treat `hint.b' as an error, which is the default. `-x' `-xexplicit' These options turn on dependency violation checking. `-xauto' This option instructs the assembler to automatically insert stop bits where necessary to remove dependency violations. This is the default mode. `-xnone' This option turns off dependency violation checking. `-xdebug' This turns on debug output intended to help tracking down bugs in the dependency violation checker. `-xdebugn' This is a shortcut for -xnone -xdebug. `-xdebugx' This is a shortcut for -xexplicit -xdebug.  File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 9.16.2 Syntax ------------- The assembler syntax closely follows the IA-64 Assembly Language Reference Guide. * Menu: * IA-64-Chars:: Special Characters * IA-64-Regs:: Register Names * IA-64-Bits:: Bit Names * IA-64-Relocs:: Relocations  File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 9.16.2.1 Special Characters ........................... `//' is the line comment token. `;' can be used instead of a newline to separate statements.  File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 9.16.2.2 Register Names ....................... The 128 integer registers are referred to as `rN'. The 128 floating-point registers are referred to as `fN'. The 128 application registers are referred to as `arN'. The 128 control registers are referred to as `crN'. The 64 one-bit predicate registers are referred to as `pN'. The 8 branch registers are referred to as `bN'. In addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' (`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), `ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). For convenience, the assembler also defines aliases for all named application and control registers. For example, `ar.bsp' refers to the register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to the end-of-interrupt register (`cr67').  File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 9.16.2.3 IA-64 Processor-Status-Register (PSR) Bit Names ........................................................ The assembler defines bit masks for each of the bits in the IA-64 processor status register. For example, `psr.ic' corresponds to a value of 0x2000. These masks are primarily intended for use with the `ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere else where an integer constant is expected.  File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 9.16.2.4 Relocations .................... In addition to the standard IA-64 relocations, the following relocations are implemented by `as': `@slotcount(V)' Convert the address offset V into a slot count. This pseudo function is available only on VMS. The expression V must be known at assembly time: it can't reference undefined symbols or symbols in different sections.  File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 9.16.3 Opcodes -------------- For detailed information on the IA-64 machine instruction set, see the IA-64 Architecture Handbook (http://developer.intel.com/design/itanium/arch_spec.htm).  File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 9.17 IP2K Dependent Features ============================ * Menu: * IP2K-Opts:: IP2K Options  File: as.info, Node: IP2K-Opts, Up: IP2K-Dependent 9.17.1 IP2K Options ------------------- The Ubicom IP2K version of `as' has a few machine dependent options: `-mip2022ext' `as' can assemble the extended IP2022 instructions, but it will only do so if this is specifically allowed via this command line option. `-mip2022' This option restores the assembler's default behaviour of not permitting the extended IP2022 instructions to be assembled.  File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 9.18 LM32 Dependent Features ============================ * Menu: * LM32 Options:: Options * LM32 Syntax:: Syntax * LM32 Opcodes:: Opcodes  File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 9.18.1 Options -------------- `-mmultiply-enabled' Enable multiply instructions. `-mdivide-enabled' Enable divide instructions. `-mbarrel-shift-enabled' Enable barrel-shift instructions. `-msign-extend-enabled' Enable sign extend instructions. `-muser-enabled' Enable user defined instructions. `-micache-enabled' Enable instruction cache related CSRs. `-mdcache-enabled' Enable data cache related CSRs. `-mbreak-enabled' Enable break instructions. `-mall-enabled' Enable all instructions and CSRs.  File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 9.18.2 Syntax ------------- * Menu: * LM32-Regs:: Register Names * LM32-Modifiers:: Relocatable Expression Modifiers  File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 9.18.2.1 Register Names ....................... LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'. The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp' - `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'. LM32 has the following Control and Status Registers (CSRs). `IE' Interrupt enable. `IM' Interrupt mask. `IP' Interrupt pending. `ICC' Instruction cache control. `DCC' Data cache control. `CC' Cycle counter. `CFG' Configuration. `EBA' Exception base address. `DC' Debug control. `DEBA' Debug exception base address. `JTX' JTAG transmit. `JRX' JTAG receive. `BP0' Breakpoint 0. `BP1' Breakpoint 1. `BP2' Breakpoint 2. `BP3' Breakpoint 3. `WP0' Watchpoint 0. `WP1' Watchpoint 1. `WP2' Watchpoint 2. `WP3' Watchpoint 3.  File: as.info, Node: LM32-Modifiers, Prev: LM32-Regs, Up: LM32 Syntax 9.18.2.2 Relocatable Expression Modifiers ......................................... The assembler supports several modifiers when using relocatable addresses in LM32 instruction operands. The general syntax is the following: modifier(relocatable-expression) `lo' This modifier allows you to use bits 0 through 15 of an address expression as 16 bit relocatable expression. `hi' This modifier allows you to use bits 16 through 23 of an address expression as 16 bit relocatable expression. For example ori r4, r4, lo(sym+10) orhi r4, r4, hi(sym+10) `gp' This modified creates a 16-bit relocatable expression that is the offset of the symbol from the global pointer. mva r4, gp(sym) `got' This modifier places a symbol in the GOT and creates a 16-bit relocatable expression that is the offset into the GOT of this symbol. lw r4, (gp+got(sym)) `gotofflo16' This modifier allows you to use the bits 0 through 15 of an address which is an offset from the GOT. `gotoffhi16' This modifier allows you to use the bits 16 through 31 of an address which is an offset from the GOT. orhi r4, r4, gotoffhi16(lsym) addi r4, r4, gotofflo16(lsym)  File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 9.18.3 Opcodes -------------- For detailed information on the LM32 machine instruction set, see `http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'. `as' implements all the standard LM32 opcodes.  File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 9.19 M32C Dependent Features ============================ `as' can assemble code for several different members of the Renesas M32C family. Normally the default is to assemble code for the M16C microprocessor. The `-m32c' option may be used to change the default to the M32C microprocessor. * Menu: * M32C-Opts:: M32C Options * M32C-Modifiers:: Symbolic Operand Modifiers  File: as.info, Node: M32C-Opts, Next: M32C-Modifiers, Up: M32C-Dependent 9.19.1 M32C Options ------------------- The Renesas M32C version of `as' has these machine-dependent options: `-m32c' Assemble M32C instructions. `-m16c' Assemble M16C instructions (default). `-relax' Enable support for link-time relaxations. `-h-tick-hex' Support H'00 style hex constants in addition to 0x00 style.  File: as.info, Node: M32C-Modifiers, Prev: M32C-Opts, Up: M32C-Dependent 9.19.2 Symbolic Operand Modifiers --------------------------------- The assembler supports several modifiers when using symbol addresses in M32C instruction operands. The general syntax is the following: %modifier(symbol) `%dsp8' `%dsp16' These modifiers override the assembler's assumptions about how big a symbol's address is. Normally, when it sees an operand like `sym[a0]' it assumes `sym' may require the widest displacement field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers tell it to assume the address will fit in an 8 or 16 bit (respectively) unsigned displacement. Note that, of course, if it doesn't actually fit you will get linker errors. Example: mov.w %dsp8(sym)[a0],r1 mov.b #0,%dsp8(sym)[a0] `%hi8' This modifier allows you to load bits 16 through 23 of a 24 bit address into an 8 bit register. This is useful with, for example, the M16C `smovf' instruction, which expects a 20 bit address in `r1h' and `a0'. Example: mov.b #%hi8(sym),r1h mov.w #%lo16(sym),a0 smovf.b `%lo16' Likewise, this modifier allows you to load bits 0 through 15 of a 24 bit address into a 16 bit register. `%hi16' This modifier allows you to load bits 16 through 31 of a 32 bit address into a 16 bit register. While the M32C family only has 24 bits of address space, it does support addresses in pairs of 16 bit registers (like `a1a0' for the `lde' instruction). This modifier is for loading the upper half in such cases. Example: mov.w #%hi16(sym),a1 mov.w #%lo16(sym),a0 ... lde.w [a1a0],r1  File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 9.20 M32R Dependent Features ============================ * Menu: * M32R-Opts:: M32R Options * M32R-Directives:: M32R Directives * M32R-Warnings:: M32R Warnings  File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 9.20.1 M32R Options ------------------- The Renease M32R version of `as' has a few machine dependent options: `-m32rx' `as' can assemble code for several different members of the Renesas M32R family. Normally the default is to assemble code for the M32R microprocessor. This option may be used to change the default to the M32RX microprocessor, which adds some more instructions to the basic M32R instruction set, and some additional parameters to some of the original instructions. `-m32r2' This option changes the target processor to the the M32R2 microprocessor. `-m32r' This option can be used to restore the assembler's default behaviour of assembling for the M32R microprocessor. This can be useful if the default has been changed by a previous command line option. `-little' This option tells the assembler to produce little-endian code and data. The default is dependent upon how the toolchain was configured. `-EL' This is a synonym for _-little_. `-big' This option tells the assembler to produce big-endian code and data. `-EB' This is a synonum for _-big_. `-KPIC' This option specifies that the output of the assembler should be marked as position-independent code (PIC). `-parallel' This option tells the assembler to attempts to combine two sequential instructions into a single, parallel instruction, where it is legal to do so. `-no-parallel' This option disables a previously enabled _-parallel_ option. `-no-bitinst' This option disables the support for the extended bit-field instructions provided by the M32R2. If this support needs to be re-enabled the _-bitinst_ switch can be used to restore it. `-O' This option tells the assembler to attempt to optimize the instructions that it produces. This includes filling delay slots and converting sequential instructions into parallel ones. This option implies _-parallel_. `-warn-explicit-parallel-conflicts' Instructs `as' to produce warning messages when questionable parallel instructions are encountered. This option is enabled by default, but `gcc' disables it when it invokes `as' directly. Questionable instructions are those whose behaviour would be different if they were executed sequentially. For example the code fragment `mv r1, r2 || mv r3, r1' produces a different result from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 and r3. `-Wp' This is a shorter synonym for the _-warn-explicit-parallel-conflicts_ option. `-no-warn-explicit-parallel-conflicts' Instructs `as' not to produce warning messages when questionable parallel instructions are encountered. `-Wnp' This is a shorter synonym for the _-no-warn-explicit-parallel-conflicts_ option. `-ignore-parallel-conflicts' This option tells the assembler's to stop checking parallel instructions for constraint violations. This ability is provided for hardware vendors testing chip designs and should not be used under normal circumstances. `-no-ignore-parallel-conflicts' This option restores the assembler's default behaviour of checking parallel instructions to detect constraint violations. `-Ip' This is a shorter synonym for the _-ignore-parallel-conflicts_ option. `-nIp' This is a shorter synonym for the _-no-ignore-parallel-conflicts_ option. `-warn-unmatched-high' This option tells the assembler to produce a warning message if a `.high' pseudo op is encountered without a matching `.low' pseudo op. The presence of such an unmatched pseudo op usually indicates a programming error. `-no-warn-unmatched-high' Disables a previously enabled _-warn-unmatched-high_ option. `-Wuh' This is a shorter synonym for the _-warn-unmatched-high_ option. `-Wnuh' This is a shorter synonym for the _-no-warn-unmatched-high_ option.  File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 9.20.2 M32R Directives ---------------------- The Renease M32R version of `as' has a few architecture specific directives: `low EXPRESSION' The `low' directive computes the value of its expression and places the lower 16-bits of the result into the immediate-field of the instruction. For example: or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred `high EXPRESSION' The `high' directive computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. For example: seth r0, #high(0x12345678) ; compute r0 = 0x12340000 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred `shigh EXPRESSION' The `shigh' directive is very similar to the `high' directive. It also computes the value of its expression and places the upper 16-bits of the result into the immediate-field of the instruction. The difference is that `shigh' also checks to see if the lower 16-bits could be interpreted as a signed number, and if so it assumes that a borrow will occur from the upper-16 bits. To compensate for this the `shigh' directive pre-biases the upper 16 bit value by adding one to it. For example: For example: seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 In the second example the lower 16-bits are 0x8000. If these are treated as a signed value and sign extended to 32-bits then the value becomes 0xffff8000. If this value is then added to 0x00010000 then the result is 0x00008000. This behaviour is to allow for the different semantics of the `or3' and `add3' instructions. The `or3' instruction treats its 16-bit immediate argument as unsigned whereas the `add3' treats its 16-bit immediate as a signed value. So for example: seth r0, #shigh(0x00008000) add3 r0, r0, #low(0x00008000) Produces the correct result in r0, whereas: seth r0, #shigh(0x00008000) or3 r0, r0, #low(0x00008000) Stores 0xffff8000 into r0. Note - the `shigh' directive does not know where in the assembly source code the lower 16-bits of the value are going set, so it cannot check to make sure that an `or3' instruction is being used rather than an `add3' instruction. It is up to the programmer to make sure that correct directives are used. `.m32r' The directive performs a similar thing as the _-m32r_ command line option. It tells the assembler to only accept M32R instructions from now on. An instructions from later M32R architectures are refused. `.m32rx' The directive performs a similar thing as the _-m32rx_ command line option. It tells the assembler to start accepting the extra instructions in the M32RX ISA as well as the ordinary M32R ISA. `.m32r2' The directive performs a similar thing as the _-m32r2_ command line option. It tells the assembler to start accepting the extra instructions in the M32R2 ISA as well as the ordinary M32R ISA. `.little' The directive performs a similar thing as the _-little_ command line option. It tells the assembler to start producing little-endian code and data. This option should be used with care as producing mixed-endian binary files is fraught with danger. `.big' The directive performs a similar thing as the _-big_ command line option. It tells the assembler to start producing big-endian code and data. This option should be used with care as producing mixed-endian binary files is fraught with danger.  File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 9.20.3 M32R Warnings -------------------- There are several warning and error messages that can be produced by `as' which are specific to the M32R: `output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the left hand instruction is used as an input register in the right hand instruction. For example in this code fragment `mv r1, r2 || neg r3, r1' register r1 is the destination of the move instruction and the input to the neg instruction. `output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' This message is only produced if warnings for explicit parallel conflicts have been enabled. It indicates that the assembler has encountered a parallel instruction in which the destination register of the right hand instruction is used as an input register in the left hand instruction. For example in this code fragment `mv r1, r2 || neg r2, r3' register r2 is the destination of the neg instruction and the input to the move instruction. `instruction `...' is for the M32RX only' This message is produced when the assembler encounters an instruction which is only supported by the M32Rx processor, and the `-m32rx' command line flag has not been specified to allow assembly of such instructions. `unknown instruction `...'' This message is produced when the assembler encounters an instruction which it does not recognize. `only the NOP instruction can be issued in parallel on the m32r' This message is produced when the assembler encounters a parallel instruction which does not involve a NOP instruction and the `-m32rx' command line flag has not been specified. Only the M32Rx processor is able to execute two instructions in parallel. `instruction `...' cannot be executed in parallel.' This message is produced when the assembler encounters a parallel instruction which is made up of one or two instructions which cannot be executed in parallel. `Instructions share the same execution pipeline' This message is produced when the assembler encounters a parallel instruction whoes components both use the same execution pipeline. `Instructions write to the same destination register.' This message is produced when the assembler encounters a parallel instruction where both components attempt to modify the same register. For example these code fragments will produce this message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx r3, r4' (Both write to the condition bit)  File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 9.21 M680x0 Dependent Features ============================== * Menu: * M68K-Opts:: M680x0 Options * M68K-Syntax:: Syntax * M68K-Moto-Syntax:: Motorola Syntax * M68K-Float:: Floating Point * M68K-Directives:: 680x0 Machine Directives * M68K-opcodes:: Opcodes  File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 9.21.1 M680x0 Options --------------------- The Motorola 680x0 version of `as' has a few machine dependent options: `-march=ARCHITECTURE' This option specifies a target architecture. The following architectures are recognized: `68000', `68010', `68020', `68030', `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and `cfv4e'. `-mcpu=CPU' This option specifies a target cpu. When used in conjunction with the `-march' option, the cpu must be within the specified architecture. Also, the generic features of the architecture are used for instruction generation, rather than those of the specific chip. `-m[no-]68851' `-m[no-]68881' `-m[no-]div' `-m[no-]usp' `-m[no-]float' `-m[no-]mac' `-m[no-]emac' Enable or disable various architecture specific features. If a chip or architecture by default supports an option (for instance `-march=isaaplus' includes the `-mdiv' option), explicitly disabling the option will override the default. `-l' You can use the `-l' option to shorten the size of references to undefined symbols. If you do not use the `-l' option, references to undefined symbols are wide enough for a full `long' (32 bits). (Since `as' cannot know where these symbols end up, `as' can only allocate space for the linker to fill in later. Since `as' does not know how far away these symbols are, it allocates as much space as it can.) If you use this option, the references are only one word wide (16 bits). This may be useful if you want the object file to be as small as possible, and you know that the relevant symbols are always less than 17 bits away. `--register-prefix-optional' For some configurations, especially those where the compiler normally does not prepend an underscore to the names of user variables, the assembler requires a `%' before any use of a register name. This is intended to let the assembler distinguish between C variables and functions named `a0' through `a7', and so on. The `%' is always accepted, but is not required for certain configurations, notably `sun3'. The `--register-prefix-optional' option may be used to permit omitting the `%' even for configurations for which it is normally required. If this is done, it will generally be impossible to refer to C variables and functions with the same names as register names. `--bitwise-or' Normally the character `|' is treated as a comment character, which means that it can not be used in expressions. The `--bitwise-or' option turns `|' into a normal character. In this mode, you must either use C style comments, or start comments with a `#' character at the beginning of a line. `--base-size-default-16 --base-size-default-32' If you use an addressing mode with a base register without specifying the size, `as' will normally use the full 32 bit value. For example, the addressing mode `%a0@(%d0)' is equivalent to `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to tell `as' to default to using the 16 bit value. In this case, `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the `--base-size-default-32' option to restore the default behaviour. `--disp-size-default-16 --disp-size-default-32' If you use an addressing mode with a displacement, and the value of the displacement is not known, `as' will normally assume that the value is 32 bits. For example, if the symbol `disp' has not been defined, `as' will assemble the addressing mode `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use the `--disp-size-default-16' option to tell `as' to instead assume that the displacement is 16 bits. In this case, `as' will assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You may use the `--disp-size-default-32' option to restore the default behaviour. `--pcrel' Always keep branches PC-relative. In the M680x0 architecture all branches are defined as PC-relative. However, on some processors they are limited to word displacements maximum. When `as' needs a long branch that is not available, it normally emits an absolute jump instead. This option disables this substitution. When this option is given and no long branches are available, only word branches will be emitted. An error message will be generated if a word branch cannot reach its target. This option has no effect on 68020 and other processors that have long branches. *note Branch Improvement: M68K-Branch. `-m68000' `as' can assemble code for several different members of the Motorola 680x0 family. The default depends upon how `as' was configured when it was built; normally, the default is to assemble code for the 68020 microprocessor. The following options may be used to change the default. These options control which instructions and addressing modes are permitted. The members of the 680x0 family are very similar. For detailed information about the differences, see the Motorola manuals. `-m68000' `-m68ec000' `-m68hc000' `-m68hc001' `-m68008' `-m68302' `-m68306' `-m68307' `-m68322' `-m68356' Assemble for the 68000. `-m68008', `-m68302', and so on are synonyms for `-m68000', since the chips are the same from the point of view of the assembler. `-m68010' Assemble for the 68010. `-m68020' `-m68ec020' Assemble for the 68020. This is normally the default. `-m68030' `-m68ec030' Assemble for the 68030. `-m68040' `-m68ec040' Assemble for the 68040. `-m68060' `-m68ec060' Assemble for the 68060. `-mcpu32' `-m68330' `-m68331' `-m68332' `-m68333' `-m68334' `-m68336' `-m68340' `-m68341' `-m68349' `-m68360' Assemble for the CPU32 family of chips. `-m5200' `-m5202' `-m5204' `-m5206' `-m5206e' `-m521x' `-m5249' `-m528x' `-m5307' `-m5407' `-m547x' `-m548x' `-mcfv4' `-mcfv4e' Assemble for the ColdFire family of chips. `-m68881' `-m68882' Assemble 68881 floating point instructions. This is the default for the 68020, 68030, and the CPU32. The 68040 and 68060 always support floating point instructions. `-mno-68881' Do not assemble 68881 floating point instructions. This is the default for 68000 and the 68010. The 68040 and 68060 always support floating point instructions, even if this option is used. `-m68851' Assemble 68851 MMU instructions. This is the default for the 68020, 68030, and 68060. The 68040 accepts a somewhat different set of MMU instructions; `-m68851' and `-m68040' should not be used together. `-mno-68851' Do not assemble 68851 MMU instructions. This is the default for the 68000, 68010, and the CPU32. The 68040 accepts a somewhat different set of MMU instructions.  File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 9.21.2 Syntax ------------- This syntax for the Motorola 680x0 was developed at MIT. The 680x0 version of `as' uses instructions names and syntax compatible with the Sun assembler. Intervening periods are ignored; for example, `movl' is equivalent to `mov.l'. In the following table APC stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), a suppressed address register (`%za0' through `%za7'), or it may be omitted entirely. The use of SIZE means one of `w' or `l', and it may be omitted, along with the leading colon, unless a scale is also specified. The use of SCALE means one of `1', `2', `4', or `8', and it may always be omitted along with the leading colon. The following addressing modes are understood: "Immediate" `#NUMBER' "Data Register" `%d0' through `%d7' "Address Register" `%a0' through `%a7' `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is also known as `%fp', the Frame Pointer. "Address Register Indirect" `%a0@' through `%a7@' "Address Register Postincrement" `%a0@+' through `%a7@+' "Address Register Predecrement" `%a0@-' through `%a7@-' "Indirect Plus Offset" `APC@(NUMBER)' "Index" `APC@(NUMBER,REGISTER:SIZE:SCALE)' The NUMBER may be omitted. "Postindex" `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' The ONUMBER or the REGISTER, but not both, may be omitted. "Preindex" `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' The NUMBER may be omitted. Omitting the REGISTER produces the Postindex addressing mode. "Absolute" `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'.  File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 9.21.3 Motorola Syntax ---------------------- The standard Motorola syntax for this chip differs from the syntax already discussed (*note Syntax: M68K-Syntax.). `as' can accept Motorola syntax for operands, even if MIT syntax is used for other operands in the same instruction. The two kinds of syntax are fully compatible. In the following table APC stands for any of the address registers (`%a0' through `%a7'), the program counter (`%pc'), the zero-address relative to the program counter (`%zpc'), or a suppressed address register (`%za0' through `%za7'). The use of SIZE means one of `w' or `l', and it may always be omitted along with the leading dot. The use of SCALE means one of `1', `2', `4', or `8', and it may always be omitted along with the leading asterisk. The following additional addressing modes are understood: "Address Register Indirect" `(%a0)' through `(%a7)' `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is also known as `%fp', the Frame Pointer. "Address Register Postincrement" `(%a0)+' through `(%a7)+' "Address Register Predecrement" `-(%a0)' through `-(%a7)' "Indirect Plus Offset" `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. The NUMBER may also appear within the parentheses, as in `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted (with an address register, omitting the NUMBER produces Address Register Indirect mode). "Index" `NUMBER(APC,REGISTER.SIZE*SCALE)' The NUMBER may be omitted, or it may appear within the parentheses. The APC may be omitted. The REGISTER and the APC may appear in either order. If both APC and REGISTER are address registers, and the SIZE and SCALE are omitted, then the first register is taken as the base register, and the second as the index register. "Postindex" `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' The ONUMBER, or the REGISTER, or both, may be omitted. Either the NUMBER or the APC may be omitted, but not both. "Preindex" `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' The NUMBER, or the APC, or the REGISTER, or any two of them, may be omitted. The ONUMBER may be omitted. The REGISTER and the APC may appear in either order. If both APC and REGISTER are address registers, and the SIZE and SCALE are omitted, then the first register is taken as the base register, and the second as the index register.  File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 9.21.4 Floating Point --------------------- Packed decimal (P) format floating literals are not supported. Feel free to add the code! The floating point formats generated by directives are these. `.float' `Single' precision floating point constants. `.double' `Double' precision floating point constants. `.extend' `.ldouble' `Extended' precision (`long double') floating point constants.  File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 9.21.5 680x0 Machine Directives ------------------------------- In order to be compatible with the Sun assembler the 680x0 assembler understands the following directives. `.data1' This directive is identical to a `.data 1' directive. `.data2' This directive is identical to a `.data 2' directive. `.even' This directive is a special case of the `.align' directive; it aligns the output to an even byte boundary. `.skip' This directive is identical to a `.space' directive. `.arch NAME' Select the target architecture and extension features. Valid values for NAME are the same as for the `-march' command line option. This directive cannot be specified after any instructions have been assembled. If it is given multiple times, or in conjunction with the `-march' option, all uses must be for the same architecture and extension set. `.cpu NAME' Select the target cpu. Valid valuse for NAME are the same as for the `-mcpu' command line option. This directive cannot be specified after any instructions have been assembled. If it is given multiple times, or in conjunction with the `-mopt' option, all uses must be for the same cpu.  File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 9.21.6 Opcodes -------------- * Menu: * M68K-Branch:: Branch Improvement * M68K-Chars:: Special Characters  File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 9.21.6.1 Branch Improvement ........................... Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting `j' for `b' at the start of a Motorola mnemonic. The following table summarizes the pseudo-operations. A `*' flags cases that are more fully described after the table: Displacement +------------------------------------------------------------ | 68020 68000/10, not PC-relative OK Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** +------------------------------------------------------------ jbsr |bsrs bsrw bsrl jsr jra |bras braw bral jmp * jXX |bXXs bXXw bXXl bNXs;jmp * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp fjXX | N/A fbXXw fbXXl N/A XX: condition NX: negative of condition XX `*'--see full description below `**'--this expansion mode is disallowed by `--pcrel' `jbsr' `jra' These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. This instruction will be a byte or word branch is that is sufficient. Otherwise, a long branch will be emitted if available. If no long branches are available and the `--pcrel' option is not given, an absolute long jump will be emitted instead. If no long branches are available, the `--pcrel' option is given, and a word branch cannot reach the target, an error message is generated. In addition to standard branch operands, `as' allows these pseudo-operations to have all operands that are allowed for jsr and jmp, substituting these instructions if the operand given is not valid for a branch instruction. `jXX' Here, `jXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is: jhi jls jcc jcs jne jeq jvc jvs jpl jmi jge jlt jgt jle Usually, each of these pseudo-operations expands to a single branch instruction. However, if a word branch is not sufficient, no long branches are available, and the `--pcrel' option is not given, `as' issues a longer code fragment in terms of NX, the opposite condition to XX. For example, under these conditions: jXX foo gives bNXs oof jmp foo oof: `dbXX' The full family of pseudo-operations covered here is dbhi dbls dbcc dbcs dbne dbeq dbvc dbvs dbpl dbmi dbge dblt dbgt dble dbf dbra dbt Motorola `dbXX' instructions allow word displacements only. When a word displacement is sufficient, each of these pseudo-operations expands to the corresponding Motorola instruction. When a word displacement is not sufficient and long branches are available, when the source reads `dbXX foo', `as' emits dbXX oo1 bras oo2 oo1:bral foo oo2: If, however, long branches are not available and the `--pcrel' option is not given, `as' emits dbXX oo1 bras oo2 oo1:jmp foo oo2: `fjXX' This family includes fjne fjeq fjge fjlt fjgt fjle fjf fjt fjgl fjgle fjnge fjngl fjngle fjngt fjnle fjnlt fjoge fjogl fjogt fjole fjolt fjor fjseq fjsf fjsne fjst fjueq fjuge fjugt fjule fjult fjun Each of these pseudo-operations always expands to a single Motorola coprocessor branch instruction, word or long. All Motorola coprocessor branch instructions allow both word and long displacements.  File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 9.21.6.2 Special Characters ........................... The immediate character is `#' for Sun compatibility. The line-comment character is `|' (unless the `--bitwise-or' option is used). If a `#' appears at the beginning of a line, it is treated as a comment unless it looks like `# line file', in which case it is treated normally.  File: as.info, Node: M68HC11-Dependent, Next: MicroBlaze-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 9.22 M68HC11 and M68HC12 Dependent Features =========================================== * Menu: * M68HC11-Opts:: M68HC11 and M68HC12 Options * M68HC11-Syntax:: Syntax * M68HC11-Modifiers:: Symbolic Operand Modifiers * M68HC11-Directives:: Assembler Directives * M68HC11-Float:: Floating Point * M68HC11-opcodes:: Opcodes  File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 9.22.1 M68HC11 and M68HC12 Options ---------------------------------- The Motorola 68HC11 and 68HC12 version of `as' have a few machine dependent options. `-m68hc11' This option switches the assembler in the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11. `-m68hc12' This option switches the assembler in the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications. `-m68hcs12' This option switches the assembler in the M68HCS12 mode. This mode is similar to `-m68hc12' but specifies to assemble for the 68HCS12 series. The only difference is on the assembling of the `movb' and `movw' instruction when a PC-relative operand is used. `-mshort' This option controls the ABI and indicates to use a 16-bit integer ABI. It has no effect on the assembled instructions. This is the default. `-mlong' This option controls the ABI and indicates to use a 32-bit integer ABI. `-mshort-double' This option controls the ABI and indicates to use a 32-bit float ABI. This is the default. `-mlong-double' This option controls the ABI and indicates to use a 64-bit float ABI. `--strict-direct-mode' You can use the `--strict-direct-mode' option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For example, the `clr' instruction does not support direct page mode addressing. When it is used with the direct page mode, `as' will ignore it and generate an absolute addressing. This option prevents `as' from doing this, and the wrong usage of the direct page mode will raise an error. `--short-branches' The `--short-branches' option turns off the translation of relative branches into absolute branches when the branch offset is out of range. By default `as' transforms the relative branch (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch when the offset is out of the -128 .. 127 range. In that case, the `bsr' instruction is translated into a `jsr', the `bra' instruction is translated into a `jmp' and the conditional branches instructions are inverted and followed by a `jmp'. This option disables these translations and `as' will generate an error if a relative branch is out of range. This option does not affect the optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes. `--force-long-branches' The `--force-long-branches' option forces the translation of relative branches into absolute branches. This option does not affect the optimization associated to the `jbra', `jbsr' and `jbXX' pseudo opcodes. `--print-insn-syntax' You can use the `--print-insn-syntax' option to obtain the syntax description of the instruction when an error is detected. `--print-opcodes' The `--print-opcodes' option prints the list of all the instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction. The list is printed in alphabetical order. Once the list is printed `as' exits. `--generate-example' The `--generate-example' option is similar to `--print-opcodes' but it generates an example for each instruction instead.  File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 9.22.2 Syntax ------------- In the M68HC11 syntax, the instruction name comes first and it may be followed by one or several operands (up to three). Operands are separated by comma (`,'). In the normal mode, `as' will complain if too many operands are specified for a given instruction. In the MRI mode (turned on with `-M' option), it will treat them as comments. Example: inx lda #23 bset 2,x #4 brclr *bot #8 foo The following addressing modes are understood for 68HC11 and 68HC12: "Immediate" `#NUMBER' "Address Register" `NUMBER,X', `NUMBER,Y' The NUMBER may be omitted in which case 0 is assumed. "Direct Addressing mode" `*SYMBOL', or `*DIGITS' "Absolute" `SYMBOL', or `DIGITS' The M68HC12 has other more complex addressing modes. All of them are supported and they are represented below: "Constant Offset Indexed Addressing Mode" `NUMBER,REG' The NUMBER may be omitted in which case 0 is assumed. The register can be either `X', `Y', `SP' or `PC'. The assembler will use the smaller post-byte definition according to the constant value (5-bit constant offset, 9-bit constant offset or 16-bit constant offset). If the constant is not known by the assembler it will use the 16-bit constant offset post-byte and the value will be resolved at link time. "Offset Indexed Indirect" `[NUMBER,REG]' The register can be either `X', `Y', `SP' or `PC'. "Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' The number must be in the range `-8'..`+8' and must not be 0. The register can be either `X', `Y', `SP' or `PC'. "Accumulator Offset" `ACC,REG' The accumulator register can be either `A', `B' or `D'. The register can be either `X', `Y', `SP' or `PC'. "Accumulator D offset indexed-indirect" `[D,REG]' The register can be either `X', `Y', `SP' or `PC'. For example: ldab 1024,sp ldd [10,x] orab 3,+x stab -2,y- ldx a,pc sty [d,sp]  File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 9.22.3 Symbolic Operand Modifiers --------------------------------- The assembler supports several modifiers when using symbol addresses in 68HC11 and 68HC12 instruction operands. The general syntax is the following: %modifier(symbol) `%addr' This modifier indicates to the assembler and linker to use the 16-bit physical address corresponding to the symbol. This is intended to be used on memory window systems to map a symbol in the memory bank window. If the symbol is in a memory expansion part, the physical address corresponds to the symbol address within the memory bank window. If the symbol is not in a memory expansion part, this is the symbol address (using or not using the %addr modifier has no effect in that case). `%page' This modifier indicates to use the memory page number corresponding to the symbol. If the symbol is in a memory expansion part, its page number is computed by the linker as a number used to map the page containing the symbol in the memory bank window. If the symbol is not in a memory expansion part, the page number is 0. `%hi' This modifier indicates to use the 8-bit high part of the physical address of the symbol. `%lo' This modifier indicates to use the 8-bit low part of the physical address of the symbol. For example a 68HC12 call to a function `foo_example' stored in memory expansion part could be written as follows: call %addr(foo_example),%page(foo_example) and this is equivalent to call foo_example And for 68HC11 it could be written as follows: ldab #%page(foo_example) stab _page_switch jsr %addr(foo_example)  File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 9.22.4 Assembler Directives --------------------------- The 68HC11 and 68HC12 version of `as' have the following specific assembler directives: `.relax' The relax directive is used by the `GNU Compiler' to emit a specific relocation to mark a group of instructions for linker relaxation. The sequence of instructions within the group must be known to the linker so that relaxation can be performed. `.mode [mshort|mlong|mshort-double|mlong-double]' This directive specifies the ABI. It overrides the `-mshort', `-mlong', `-mshort-double' and `-mlong-double' options. `.far SYMBOL' This directive marks the symbol as a `far' symbol meaning that it uses a `call/rtc' calling convention as opposed to `jsr/rts'. During a final link, the linker will identify references to the `far' symbol and will verify the proper calling convention. `.interrupt SYMBOL' This directive marks the symbol as an interrupt entry point. This information is then used by the debugger to correctly unwind the frame across interrupts. `.xrefb SYMBOL' This directive is defined for compatibility with the `Specification for Motorola 8 and 16-Bit Assembly Language Input Standard' and is ignored.  File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 9.22.5 Floating Point --------------------- Packed decimal (P) format floating literals are not supported. Feel free to add the code! The floating point formats generated by directives are these. `.float' `Single' precision floating point constants. `.double' `Double' precision floating point constants. `.extend' `.ldouble' `Extended' precision (`long double') floating point constants.  File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 9.22.6 Opcodes -------------- * Menu: * M68HC11-Branch:: Branch Improvement  File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 9.22.6.1 Branch Improvement ........................... Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by prepending `j' to the start of Motorola mnemonic. These pseudo opcodes are not affected by the `--short-branches' or `--force-long-branches' options. The following table summarizes the pseudo-operations. Displacement Width +-------------------------------------------------------------+ | Options | | --short-branches --force-long-branches | +--------------------------+----------------------------------+ Op |BYTE WORD | BYTE WORD | +--------------------------+----------------------------------+ bsr | bsr | jsr | bra | bra | jmp | jbsr | bsr jsr | bsr jsr | jbra | bra jmp | bra jmp | bXX | bXX | bNX +3; jmp | jbXX | bXX bNX +3; | bXX bNX +3; jmp | | jmp | | +--------------------------+----------------------------------+ XX: condition NX: negative of condition XX `jbsr' `jbra' These are the simplest jump pseudo-operations; they always map to one particular machine instruction, depending on the displacement to the branch target. `jbXX' Here, `jbXX' stands for an entire family of pseudo-operations, where XX is a conditional branch or condition-code test. The full list of pseudo-ops in this family is: jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo jbcs jbne jblt jble jbls jbvc jbmi For the cases of non-PC relative displacements and long displacements, `as' issues a longer code fragment in terms of NX, the opposite condition to XX. For example, for the non-PC relative case: jbXX foo gives bNXs oof jmp foo oof:  File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 9.23 MicroBlaze Dependent Features ================================== The Xilinx MicroBlaze processor family includes several variants, all using the same core instruction set. This chapter covers features of the GNU assembler that are specific to the MicroBlaze architecture. For details about the MicroBlaze instruction set, please see the `MicroBlaze Processor Reference Guide (UG081)' available at www.xilinx.com. * Menu: * MicroBlaze Directives:: Directives for MicroBlaze Processors.  File: as.info, Node: MicroBlaze Directives, Up: MicroBlaze-Dependent 9.23.1 Directives ----------------- A number of assembler directives are available for MicroBlaze. `.data8 EXPRESSION,...' This directive is an alias for `.byte'. Each expression is assembled into an eight-bit value. `.data16 EXPRESSION,...' This directive is an alias for `.hword'. Each expression is assembled into an 16-bit value. `.data32 EXPRESSION,...' This directive is an alias for `.word'. Each expression is assembled into an 32-bit value. `.ent NAME[,LABEL]' This directive is an alias for `.func' denoting the start of function NAME at (optional) LABEL. `.end NAME[,LABEL]' This directive is an alias for `.endfunc' denoting the end of function NAME. `.gpword LABEL,...' This directive is an alias for `.rva'. The resolved address of LABEL is stored in the data section. `.weakext LABEL' Declare that LABEL is a weak external symbol. `.rodata' Switch to .rodata section. Equivalent to `.section .rodata' `.sdata2' Switch to .sdata2 section. Equivalent to `.section .sdata2' `.sdata' Switch to .sdata section. Equivalent to `.section .sdata' `.bss' Switch to .bss section. Equivalent to `.section .bss' `.sbss' Switch to .sbss section. Equivalent to `.section .sbss'  File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 9.24 MIPS Dependent Features ============================ GNU `as' for MIPS architectures supports several different MIPS processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For information about the MIPS instruction set, see `MIPS RISC Architecture', by Kane and Heindrich (Prentice-Hall). For an overview of MIPS assembly conventions, see "Appendix D: Assembly Language Programming" in the same work. * Menu: * MIPS Opts:: Assembler options * MIPS Object:: ECOFF object code * MIPS Stabs:: Directives for debugging information * MIPS ISA:: Directives to override the ISA level * MIPS symbol sizes:: Directives to override the size of symbols * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction * MIPS option stack:: Directives to save and restore options * MIPS ASE instruction generation overrides:: Directives to control generation of MIPS ASE instructions * MIPS floating-point:: Directives to override floating-point options  File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent 9.24.1 Assembler options ------------------------ The MIPS configurations of GNU `as' support these special options: `-G NUM' This option sets the largest size of an object that can be referenced implicitly with the `gp' register. It is only accepted for targets that use ECOFF format. The default value is 8. `-EB' `-EL' Any MIPS configuration of `as' can select big-endian or little-endian output at run time (unlike the other GNU development tools, which must be configured for one or the other). Use `-EB' to select big-endian output, and `-EL' for little-endian. `-KPIC' Generate SVR4-style PIC. This option tells the assembler to generate SVR4-style position-independent macro expansions. It also tells the assembler to mark the output file as PIC. `-mvxworks-pic' Generate VxWorks PIC. This option tells the assembler to generate VxWorks-style position-independent macro expansions. `-mips1' `-mips2' `-mips3' `-mips4' `-mips5xo' `-mips32' `-mips32r2' `-mips64' `-mips64r2' Generate code for a particular MIPS Instruction Set Architecture level. `-mips1' corresponds to the R2000 and R3000 processors, `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, and `-mips4' to the R8000 and R10000 processors. `-mips5', `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 RELEASE 2 ISA processors, respectively. You can also switch instruction sets during the assembly; see *Note Directives to override the ISA level: MIPS ISA. `-mgp32' `-mfp32' Some macros have different expansions for 32-bit and 64-bit registers. The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. `-mgp32' controls the size of general-purpose registers and `-mfp32' controls the size of floating-point registers. The `.set gp=32' and `.set fp=32' directives allow the size of registers to be changed for parts of an object. The default value is restored by `.set gp=default' and `.set fp=default'. On some MIPS variants there is a 32-bit mode flag; when this flag is set, 64-bit instructions generate a trap. Also, some 32-bit OSes only save the 32-bit registers on a context switch, so it is essential never to use the 64-bit registers. `-mgp64' `-mfp64' Assume that 64-bit registers are available. This is provided in the interests of symmetry with `-mgp32' and `-mfp32'. The `.set gp=64' and `.set fp=64' directives allow the size of registers to be changed for parts of an object. The default value is restored by `.set gp=default' and `.set fp=default'. `-mips16' `-no-mips16' Generate code for the MIPS 16 processor. This is equivalent to putting `.set mips16' at the start of the assembly file. `-no-mips16' turns off this option. `-msmartmips' `-mno-smartmips' Enables the SmartMIPS extensions to the MIPS32 instruction set, which provides a number of new instructions which target smartcard and cryptographic applications. This is equivalent to putting `.set smartmips' at the start of the assembly file. `-mno-smartmips' turns off this option. `-mips3d' `-no-mips3d' Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. `-no-mips3d' turns off this option. `-mdmx' `-no-mdmx' Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. `-no-mdmx' turns off this option. `-mdsp' `-mno-dsp' Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. `-mno-dsp' turns off this option. `-mdspr2' `-mno-dspr2' Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. `-mno-dspr2' turns off this option. `-mmt' `-mno-mt' Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. `-mno-mt' turns off this option. `-mfix7000' `-mno-fix7000' Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. `-mfix-loongson2f-jump' `